
Configuration
CP6000
Page 4 - 14
© 2005 Kontron Modular Computers GmbH
ID 27942, Rev. 05
2794
2.05.UG.VC.051020/17275
8
P R E L I M I N A R Y
4.5.1.2
IPMI Interrupt Configuration Register
The IPMI interrupt configuration register holds a series of bits defining the interrupt routing for
the BMC controller.
4.5.2
Watchdog
The CP6000 has one watchdog timer. This timer is provided with a programmable timeout
ranging from 125 msec to 256 sec. Failure to strobe the watchdog timer within a set time period
results in a system reset, NMI or an interrupt. This can be configured via the register 0x284.
To enable the watchdog bit ”4” of the register 0x282 must be set. If the watchdog is enabled via
bit ”4”, this bit cannot later be cleared.
With a write access to the register 0x280 the watchdog is retriggered. Once the watchdog is
enabled, it must be continuously strobed within the terminal count period to avoid resetting the
system hardware.
The watchdog can be configured in several modes, one of which is the dual stage
configuration. If the NMI and the reset configuration bit are set (0x284 = 0x84), the watchdog
has two stages. The first stage timeout generates an NMI interrupt. If the NMI handler does not
reconfigure the watchdog, the watchdog switches to the second stage and generates a master
reset after the configured timeout elapses.
4.5.3
Watchdog Trigger
A write access triggers the watchdog.
The I/O location for the watchdog trigger is 0x280.
Table 4-17: IPMI Interrupt Configuration Register
REGISTER NAME
IPMI Interrupt Configuration Register
ACCESS
ADDRESS
0x19F
R
W
BIT POSITION
MSB
7
6
5
4
3
2
1
0
LSB
CONTENT
Res.
Res.
Res.
Res.
Res.
IPMI ISA7 IPMI ISA5 IPMI SMI
DEFAULT
0
0
0
0
0
0
0
0
BIT
NAME
VAL
DESCRIPTION
0
IPMI SMI
0
Disable SMI
1
Enable SMI
1
IPMI ISA5
0
Disable IRQ5
1
Enable IRQ5
2
IPMI ISA7
0
Disable IRQ7
1
Enable IRQ7
3
0
Reserved
4
0
Reserved
5
0
Reserved
6
0
Reserved
7
0
Reserved
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