AKD SynqNet | 6 AKD SynqNet I/O Mapping
6 AKD SynqNet I/O Mapping
The following tables show the mapping from AKD physical pin names to SynqNet logical names.
These tables show mapping for FPGAs, version 0200_00_02 and later.
6.1 General Purpose I/O
AKD Firmware
AKD Connector
AKD Pin
Name
SynqNet MPI Name
Notes
DIN1.STATE
X7-10
Digital Input
1
GPIO input "DIN 1 (HS)"
High speed opto input.
Also maps to HOME.
DIN2.STATE
X7-9
Digital Input
2
GPIO input "DIN 2 (HS)"
High speed opto input.
DIN3.STATE
X7-4
Digital Input
3
GPIO input "DIN 3"
DIN4.STATE
X7-3
Digital Input
4
GPIO input "DIN 4"
DIN5.STATE
X8-6
Digital Input
5
GPIO input "DIN 5"
Also maps to "LIMIT_
HW_POS".
DIN6.STATE
X8-5
Digital Input
6
GPIO input "DIN 6"
Also maps to "LIMIT_
HW_NEG".
DIN7.STATE
X7-2
Digital Input
7
GPIO input "DIN 7"
DIN9.STATE
DIO9.STATE
X9-1/2
Emulated
Encoder A
GPIO bidir "RS485 IO 1"
See note to enable out-
put.
DIN10.STATE
DIO10.STATE
X9-4/5
Emulated
Encoder A
GPIO bidir "RS485 IO 2"
See note to enable out-
put.
DIN11.STATE
DIO11.STATE
X7-7/8
Emulated
Encoder
Zero
GPIO bidir "RS485 IO 3"
See note to enable out-
put. Also maps to
"INDEX_
SECONDARY."
DOUT1.STATE
X7-8/7
Digital Out-
put 1
GPIO output "DOUT1"
DOUT2.STATE
X7-6/5
Digital Out-
put 2
GPIO output "DOUT1"
NA
X10-6/7
Zero
GPIO input "Analog Z
Pulse"
Also maps to "INDEX_
PRIMARY." Some
encoder types do not
use index pin.
Notes:
l
The RS485 outputs must be enabled using AKD-SQ parameters.
l
Set DRV.EMUMODE = 10 (fieldbus) for SynqNet gpio output mode.
l
Set DIO9.DIR=1, DIO10.DIR=1, DIO11.DIR=1 to enable individual outputs.
l
GPIO input "Analog Z Pulse" not supported on AKD Rev 7 control boards (AKD-SQ prototypes only).
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Kollmorgen | kdn.kollmorgen.com | October 2020