
TK-3201
8
CIRCUIT DESCRIPTION
3. PLL Frequency Synthesizer
The PLL circuit generates the first local oscillator signal for
reception and the RF signal for transmission.
1) PLL
The frequency step of the PLL circuit is 5 or 6.25kHz.
A 12.8MHz reference an oscillator signal is divided at IC1
by a fixed counter to produce oscillator (VCO) output signal
which is buffer amplified by Q2 then divided in IC1 by a
programmable counter. The divided signal is compared in
phase with the 5 or 6.25kHz reference signal from the phase
comparator in IC1. The output signal from the phase
comparator is filtered through a low-pass filter and passed
to the VCO to control the oscillator frequency.(See Fig. 4)
2) VCO
The operating frequency is generated by Q4. The oscillator
frequency is controlled by applying the VCO control voltage,
obtained from the phase comparator, to the varactor diodes
(D4 and D7 in transmit mode). The RX pin is set high in
receive mode causing Q5 turn on.
The TX pin is set high in transmit mode. The output from
Q4 is amplified by Q6 and sent to the RF amplifiers.
3) Unlock Detector
If a pulse signal appears at the LD pin of IC1, an unlock
condition occurs, and the DC voltage obtained from C4,
R5, and D1 causes the voltage applied to the microprocessor
to go low. When the microprocessor detects this condition,
the transmitter is disabled, ignoring the push-to-talk switch
input signal.
4. Transmitter System
1) Microphone Amplifier
The signal from the microphone passes through IC301.
The signal passes through the Audio processor (IC301) for
the maximum deviation adjustment and necessary process
as pre-emphasized, and goes to the VCO modulation input.
2) Drive and Final Amplifier
The signal from the T/R switch (D101 is on) is amplified by
the pre-drive (Q101) and drive amplifier (Q102) to 50mW.
The output of the drive amplifier is amplified by the RF power
amplifier (Q103) to 0.5W. The RF power amplifier consists
of two MOS FET stages. The output of the RF power
amplifier is then passed through the harmonic filter (LPF)
and antenna switch (D103 and D122) and applied to the
antenna terminal.
3) APC Circuit
The APC circuit always monitors the current flowing through
the RF power amplifier (Q103) and keeps a constant current.
The voltage drop at R127, R128 and R129 is caused by the
current flowing through the RF power amplifier and this
voltage is applied to the differential amplifier IC101(1/2).
IC101(2/2) compares the output voltage of IC101(1/2) with
the reference voltage from IC405. The output of IC101(2/2)
controls the VG of the RF power amplifier, Drive amplifier
and Pre-Drive amplifier to make both voltages the same.
The change of power high/low is carried out by the change
of the reference voltage.
PLL DATA
X1
12.8MHz
REF OSC
1/M
1/N
PLL IC IC1
PHASE
COMPARATOR
CHARGE
PUMP
LPF
6.25kHz
D4,7
Q4
TX VCO
Q6
BUFF AMP
Q9
RF AMP
RX
TX
Q2
BUFFER
Q5, 7
T/R SW
6.25kHz
LPF
Fig. 5 Microphone amplifier
IC301
IC405
LPF
QTTCXO
QTVCO
CPU
AGC
VCO
MIC
X1
TCXO
LPF
AK2346
Fig. 4 PLL circuit
Fig. 6 Drive and final amplifier and APC circuit
From
T/R SW
(D101)
DRIVE
AMP
RF
POWER AMP
LPF
ANT
SW
D103
D122
ANT
VG
VG
VD
Q102
Q103
Pre-DRIVE
AMP
Q101
VDD
RF
AMP
Q100
5T
R127
R128
R129
+B
IC101
(1/2)
IC101
(2/2)
PCTV
(IC405)