13
support 64-bit addresses which can be mapped into more than 4 GB of address space.
Local Memory
( FIFO)
PCI Express Bus
First PCI Address
First Dual Address
Transfer Size
Next Descriptor
PCI Address
Dual Address
Transfer Size
Next Descriptor
PCI Address
Dual Address
Transfer Size
Next Descriptor
Figure 3-2: Linked List of PCI Address DMA Descriptors
3�3 Trigger Source and Trigger Modes
This section details PXIe-69852 triggering operations.
Figure 3-3: Trigger Architecture of the PXIe-69852
The PXIe-69852 requires a trigger to implement acquisition of data. Configuration
of triggers
requires identification of trigger source. The PXIe-69852 supports internal software trigger,
external digital trigger, and analog trigger.
