15
3.3.5 PXI Trigger Bus
The PXIe-69852 utilizes PXI Trigger Bus Numbers 0 through 7 to act as a System Synchronization
Interface (SSI). With the interconnected bus provided by PXI Trigger Bus, multiple modules are easily
synched. When configured as input, the PXIe-69852 serves as a slave module and can accept
trigger signals from one of buses 0 through 7. When configured as output, the PXIe-69852 serves as
a master module and can output trigger signals to the PXI Trigger Bus Numbers 0 through 7.
3�3�6 Analog Trigger
An analog trigger is generated when AI input signal level is detected at the SMA connector CH0, CH1
(selected by software). The trigger level is also selected by software.
3.3.7 Trigger Export
When acquisition is initiated, a pulse synchronized with the Time- base clock asserts and is output
through trigger output, at a pulse width programmable from 50ns to 10μs via software.
3�4 Trigger Modes
Trigger modes applied to trigger sources initiate different data acquisition timings when a trigger
event occurs. The following trigger mode descriptions are applied to analog input function.
3�4�1 Post Trigger Mode
Post-trigger acquisition is applicable when data is to be collected after the trigger event, as shown.
When the operation starts, PXIe-69852 waits for a trigger event. Once the trigger signal is received,
acquisition begins. Data is generated from ADC and transferred to system memory continuously. The
acquisition stops once the total data amount reaches a predefined value.
Figure 3-5: Post-Trigger Acquisition
3�4�2 Delayed Trigger Mode
Delayed-trigger acquisition is utilized to postpone data collection after the trigger event, as shown.
When PXIe-69852 receives a trigger event, a time delay is implemented before commencing acqui-
sition. The delay is specified by a 16-bit counter value such that a maximum thereof is the period of
TIMEBASE X (2
16
), and the minimum is the Timebase period.
