JVC UX-L36V, Руководство по обслуживанию

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UX-L46V/UX-L36V
ES3880FL (IC101) : MPEG decoder
1. Terminal layout
3. Pin function
Symbol I/O Pin No. Symbol I/O Function
1
2
3
4~12
13~28
29
30
31
32~39
40
41
42
43
44
45~49
50
51
52
53
54
55~62
63
64
65
66
67
68~79
80
81
VDD
RAS#
DWE#
DA0~8
DBUS0~15
RESET#
VSS
VDD
YUV0~7
VSYNC
HSYNC
CPUCLK
PCLK2X
PCLK
AUX0~4
VSS
VDD
AUX6
AUX5
AUX7
LD0~7
LWR#
LOE#
LCS3#
LCS1#
LCS0#
LA0~11
VSS
VPP
3.3V power supply
Row address strobe
DRAM write enable
DRAM multiplexed row and column address bus
DRAM data bus
System reset
Ground
3.3V power supply
YUV[7:0] 8-bit video data bus
Vertical sync
Horizontal sync
RISC and system clock input. CPUCLK is used
only if SEL_PLL[1:0] = 00 to bypass PLL.
Doubled 54MHz pixel clock
27MHz pixel clock
Auxiliary control pins 4:0
AUX0 and AUX1 are open collectors.
Ground
3.3V power supply
Auxiliary control pins 6
Auxiliary control pins 5
Auxiliary control pins 7
RISC interface data bus
RISC interface write enable
RISC interface output enable
RISC interface chip select
RISC interface chip select
RISC interface chip select
RISC interface address bus
Ground
5.0V power supply
-
O
O
O
I/O
I
-
-
O
I/O
I/O
I
I/O
I/O
I/O
-
-
I/O
I/O
I/O
I/O
O
O
O
O
O
O
-
-
80 ~ 51
1 ~ 30
100 ~ 81
31 ~ 50
82~87
88
89
90
91
92
93
94
95
96
97
98
99
100
LA12~17
ACLK
AOUT
SEL_PLL0
ATCLK
ATFS
SEL_PLL1
DA9
DOE#
AIN
ARCLK
ARFS
TDMCLK
TDMDR
TDMFS
CAS#
VSS
RISC interface address bus
Master clock for external audio DAC
Audio interface serial data output when
selected.
System and DSCK output clock
frequency selection at reset time. The
matrix below lists the available clock
frequencies and their respective PLL
bit settings.
SEL_PLL1 SEL_PLL0 DCLK
0 0 Bypass PLL (input mode)
0 1 54MHz (output mode)Default
1 0 67.5MHz (output mode)
1 1 81.0MHz (output mode)
Audio transmit bit clock
Audio transmit frame sync
Refer to the description and matrix for
SEL_PLL0 pin 89.
DRAM multiplexed row and column
address line 9
DRAM output enable
Audio serial data input
Audio receive bit clock
Audio receive frame sync
TDM serial clock
TDM serial data receive
TDM frame sync
DRAM column address strobe
Ground
O
I/O
O
I
I/O
O
I
O
O
I
I
I
I
I
I
O
-
Pin No. Function
2. Block diagram
RISC
Processor
Misc.
Processor
Interface
Serial
Audio
Interface
LA[17:0]
LD[7:0]
LCS3#, LCS#[1:0]
LWR#
LOE#
ACLK
ATCLK
AIN
AOUT
ARFS
ATFS
ARCLK
SEL_PLL[1:0]
TDMCLK
TDMDR
TDMFS
CPUCLK
RESET#
YUV[7:0]
PCLK2X
PCLK
VSYNC
HSYNC
Screen
Display
AUX
DRAM
AUX[7:0]
RAS#
DA[9:0]
DBUS[15:0]
DOE#
DWE#
CAS#
TDM
Interface
Serial Audio
Interface
TDM
Interface
Huffman
Decoder
64x32 ROM
32x32 SRAM
Registers
DRAM Interface
2Kx32 ROM
512x32 SRAM
DRAM DMA
Controller
On Screen
Display
Video Output
MPEG
Processor