
3.12
3.13
TERMINAL
BOARD
SCHEMATIC
DIAGRAM
3.14
TERMINAL
CIRCUIT
BOARD
SIDE
B
Each
address
may
have
an
address
error
by
one
interval.
ADDRESS
TABLE
OF
BOARD
PARTS
X
axis
Y
axis
2
1
14
13
CN7
SIDE
B
FROM/TO
CPU
CN7
SC93496
1C
3-12
3-12
2C(
両面
)
3-12
IC3
IC21
IC51
IC61
IC81
Q11
Q21
D1
D16
D21
D22
D41
D51
D61
D71
D81
D82
D121
5A
2E
4C
5C
1C
2C
5D
5D
3C
4D
4D
5D
2B
4B
3B
2B
2A
5D
D122
D181
D182
R1
R16
R17
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R31
R32
R41
4E
1B
1B
5E
4C
2C
1E
4C
2E
2E
1F
1E
1E
2F
2F
1E
4E
2D
5D
R42
R51
R54
R56
R57
R58
R59
R60
R61
R64
R71
R72
R81
R82
R83
R84
R85
R86
R181
R201
5C
2B
2B
2A
2A
3B
3B
3B
4C
5B
2B
4B
1D
1C
1C
1C
1C
1B
2C
4F
R202
R611
R612
R613
R831
R832
C4
C6
C8
C14
C15
C16
C18
C20
C21
C22
C23
C24
C25
4E
5B
6B
6B
1C
1C
5F
4F
5B
2E
3C
3C
3A
3A
4D
4A
2E
1F
1E
C26
C27
C28
C29
C30
C42
C55
C56
C57
C64
C65
C72
C73
C81
C111
C112
C141
C142
C143
C171
1E
1E
2F
4E
4A
5C
3A
4B
4B
5B
5B
4B
5A
1D
4F
3E
2E
2E
2E
3C
C172
C181
C182
C201
C511
C512
C541
C542
C611
C612
C711
C712
L2
L3
L14
L15
L16
L51
L71
3C
3A
2A
4A
2B
2B
2A
3B
5B
5B
3B
3B
6E
5E
2E
2C
3A
4A
TP1
TP2
TP3
TB2
CN8
CN9
VA1
VA2
VA3
PC21
PC22
PC41
F1
1D
3F
6B
6F
3A
6D
6D
5F
5E
1D
1D
5C
6D
FL1
T1
6E
3C
1
2
3
4
5
6
POW
CIRCUIT
BOARD
A
B
C
D
E
F
FROM/TO
(Page
3-9)
FROM/TO
POW
CN9
(Page
3-11)
CPU
CN7