JVC MX-J570V, Руководство по обслуживанию

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MX-J570V/MX-J680V
1-57
Pin No Symbol and I/O Description
Video Output
157
177
155,154,152,150,148,145,143,
142
158
I/O
I
O
I/O
Horizontal sync. The decoder begins outputting pixel data for a new
horizontal line after the falling (active) edge of HSYNC.
Video clock. Clocks out data on input. VDATA[7:0]. Clock is ty-
pically 27 MHz.
Video data bus. Byte serial CbYCrY data synchronous with VCLK.
At power-up, the decoder does not drive VDATA. During boot-up,
the decoder uses configuration parameters to drive or 3-state
VDATA.
Vertical sync. Bi-directional, the decoder outputs the top border of
a new field on the first HSYNC after the falling edge of VSYNC.
VSYNC can accept vertical synchronization or top/bottom field no-
tification from an external source. (VSYNC HIGH = bottom field.
VSYNC LOW = Top field)
SDRAM/EDO/ROM interface
92
94
79
127,126,124,122-120,118,116,
114,112-110,108,106-104,102,
100-98,96
78,76,74-72,70,68,66,64,62,60-
58,56,54,53
82
128
85
84
88,90
86
80
O
O
O
O
I/O
O
O,OD,PU
O
O
O
O
O
Active LOW EDO DRAM column address strobe.
Active LOW EDO DRAM Row address strobe.
SDRAM LDQM.
Memory address.
Memory data.
SDRAM/EDO write enable. Decoder asserts active LOW to request
a write operation to the SDRAM array.
ROM chip select. Open drain signal, must be pulled-up to 3.3 volts.
Active LOW SDRAM column address.
SDRAM system clock.
Active LOW SDRAM bank select.
Active LOW SDRAM row address.
SDRAM UDQM.
Audio interface
167
161
166
169
173
171
172
O
O
O
I/O
I
I
I
PCM bit clock. Divided by 8 from DA-XCK, DA-BCK can be either
48 or 32 times the sampling clock.
Serial audio samples relative to DA-BCK clock.
PCM left-right clock. Identifies the channel for each audio sample.
The polarity is programmable.
Audio external frequency clock. Used to generate DA-BCK and DA-
LRCK. DA-XCK can be either 384 or 256 times the sampling frequ-
ency.
PCM input bit clock.
PCM input data, two channels. Serial audio samples relative to DA-
BCK clock, resulting in downmixed audio output.
PCM input left-right clock.
1.I-input, O-output, OD-open drain, PU-requires external 4.7-k pull-up resistor.
Name
HSYNC
VCLK
VDATA[7:0]
VSYNC
EDO-CAS
EDO-RAS
LDQM
MADDR[20:0]
MDATA[15:0]
MWE
ROM-CS
SD-CAS
SD-CLK
SD-CS[1:0]
SD-RAS
UDQM
DA-BCK
DA-DATA
DA-LRCK
DA-XCK
DAI-BCK
DAI-DATA
DAI-LRCK
3.Pin function(2/2)