JVC KD-LH3105, Руководство по обслуживанию

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(No.49839)1-49
• Pin function
Pin No. Symbol I/O Function
1 /RESET I Hard reset input (H:Operation L: Reset)
2 MiMD I Mode select input for MCU interface (H:IIC L:Serial)
3 /MiCS I Chip select input for MCU interface
/WE O Write-enable for external DRAM
4 /MiLP I Latch pulse input for MCU interface
/RAS O Low address strobe for external DRAM
5 MiDio I/O Data input and output for MCU interface (IIC:SDA)
6 /MiCK I Clock input for MCU interface (IIC:SCL)
7 MiACK O Acknowledge output for MCU interface
A11R O Address output-11 for external DRAM
8 VDDT - Power supply for digital circuit (3.3V)
9 SDo O Data output
10 BCKo O Bit clock output
11 LRCKo O LR clock output
12 SDi0 I Data input-0
13 BCKiA I Bit clock input-A
14 LRCKiA I LR clock input-A
15 SDi1 I Data input-1 (Address output-5 for external SRAM)
A0 O Address output-1 for external DRAM
16 BCKiB I Bit clock input-B
A1 O External DRAM address output-1
17 LRCKiB I LR clock input-B (Enable signal output for external SRAM)
A2 O Address-2 for external DRAM
18 VDD - Power supply for digital circuit (2.5V)
19 STANBY I Control input for stand-by mode (H:STB,L:Normal)
20 VSS - Ground for digital circuit
21 VSSL - Ground for DAC Lch
22 VRAL - Reference voltage for DAC Lch
23 LO O DAC Lch output
24 VDAL - Power supply for DAC Lch (2.5V)
25 VDAR - Power supply for DAC Rch (2.5V)
26 RO O DAC Rch output
27 VRAR - Reference voltage for DAC Rch
28 VSSR - Ground for DAC Rch
29 TESTP I Test terminal (H:Test mode L:Normal)
30 TXO O SPDIF output
31 Po0 O General output port-0
A3 O Address-3 for external DRAM
32 Po1 O General output port-1
A4 O Address-4 for external DRAM
33 Po2 O General output port-2
A5 O Address-5 for external DRAM
34 Po3 O General output port-3
A6 O Address-6 for external DRAM
35 VDDT - Power supply for digital circuit (3.3V)
36 Po4 O General output port-4
A7 O Address-7 for external DRAM
37 Po5 O General output port-5 (Address output-7 for external SRAM)
A8 O Address-8 for external DRAM
38 Po6 O General output port-6 (Address output-6 for external SRAM)
A9 O Address-9 for external DRAM
39 Po7 O General output port-7
40 VSS - Ground for digital circuit
41 IRQ/REQ I/O Interruption input (BS I/F:REQ output)
A11R O Address-11 for external DRAM
42 VDDM - Power supply for built-in 1Mbit SRAM (2.5V)
43 Fi0 I Flag input-0
/OE O Enable output for external up DRAM
44 Fi1 I Flag input-1
/CAS O Column address strobe for external DRAM
45 VSSM - Ground for built-in 1Mbit SRAM