Peripheral Interfaces
super
MOPS
pro
Copyright
JUMP
tec
Industrielle Computertechnik AG
Page: 35 of 93
Interrupt Enable Register
The interrupt-enable-registers are used to enable independently the four serial channel interrupts
which activates the interrupt output. To enable the interrupt output, bit3 of the modem-control-register
must be set. If bit7 of the line-control-register is set, the MSB of the baud rate-register is enabled
instead of the interrupt-enable-register .
bit number
7
6
5
4
3
2
1
0
function
possible value
X X X X
-
X
modem status
1 = interrupt enabled
X
receiver-line status
1 = interrupt enabled
X
TX-hold-reg.
empty
1 = interrupt enabled
X data ready
1 = interrupt enabled
After reset all bits are zero.
FIFO Control Register
The FIFO control register is a write only register at the same location as the interrupt ID register. This
register is used to enable and clear the FIFOs, set the receiver FIFO trigger level.
bit number
7
6
5
4
3
2
1
0
function
possible value
X X
trigger level of the
receiver FIFO
00 = 1 byte
01 = 4 bytes
10 = 8 bytes
11 = 14 bytes
X X X
-
-
X
clear transmit
FIFO
1 = clear
X
clear receive FIFO
1 = clear
X enable disable
FIFOs
1 = eanable FIFOs
0 = disable FIFOs
If bit 0 = 0 clears all bytes in the transmit and receive FIFO, it must be 1 to write to other bits in this
register. Bits 1 and 2 are self-clearing.
Floppy Connector (X4)
Pin
Signal
Function
Pin
Signal
Function
1
VCC
+ 5V
2
IDX
index
3
VCC
+ 5V
4
DS0
drive select 0
5
VCC
+ 5V
6
/DCHNG
disk change
7
NC
-
8
NC
-
9
NC
-
10
Mo0
motor on
11
NC
-
12
DIR
direction select
13
NC
-
14
STEP
step
15
GND
ground
16
WD
write data
17
GND
ground
18
WG
write gate
19
GND
ground
20
TR00
track 00
21
GND
ground
22
WP
write protect
23
GND
ground
24
RD
read data
25
GND
ground
26
SIDE
side one select
IDE Connector for 2,5" Hard Disk (X10)