JPM MPS2, Руководство пользователя

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15
MAIN BOARD -TECHNICAL DESCRIPTION
Memory Addressing
Memory addressing is used to enable the program ROM, data RAM and peripheral devices used for switch
interfacing and output driving. AII select lines tor the above devices are generated trom two Universal Logic
Arrays (ULA's).
Two discrete EPROMS's can be addressed within MPS2, their select lines being ROMSEL 1 and ROMSEL 2,
IC11 pins 20 and 21 respectively. These lines go off board to the memory card. The type of EPROM fitted, and
hence the required addressing range of ROMSEL 1 and ROMSEL 2, is set by two links on the memory board.
These links interface into the ULA as S0 and S1. These two lines allow the system to be configured for the use
of 64K (2764), 128K (27128) or 256K (27256) EPROMS.
The on-board RAM, IC23 is selected via the control lines RAM CS 1 and RAM CS 2 IC11 pins 27 and 33
respectively. This is a 2K x 8 CMOS device and is the main non-volatile store. The selection of the RAM is
controlled by both ULA 1 and ULA 2, these protect the data within the RAM against corruption in the case of
power failure. As an added safeguard IC35 (PCF 1251P) keeps the RAM disabled during power up or down.
The reset to the RAM is generated from a precision voltage reference and a comparitor, D22 and one half of
IC31. This monitors the level of the +5v line and goes low if the +5v drops below +4.5v. Thus the RAM will be
disabled before any malfunction might occur due to a low supply line. The reset system will be dealt with in
more detail in the section dealing with interrupts.
Four further memory mapped enable lines are generated by ULA 2. These are SEL 0, SEL 1, SEL 2 and SEL 3,
pins 37,36,35,34 and 4 respectively. These lines enable the peripheral interface elements, whose specific
functions will be dealt with in their relevant sections (multiplexing, input interfacing and output interfacing).
To allow tor the interfacing of slow peripheral into the system, circuitry within ULA 2 can generate a wait state
i.e. extension of the memory access time by one clock period. Selection of wait states tor the peripherals is
enabled by link 2, WAlT EN. With link 2 in wait states are disabled.
Link 1 is used to disable or enable the ready circuitry. If this link is removed, all memory cycles will have wait
states inserted. When the link is inserted only peripheral addressing will be subject to wait states. Both links are
not user selectable and are loaded at the time of board manufacture.
To allow the use of the full address range trom an external source, the ULA 2 enable lines tor I/O may be
disabled by setting I/O select disable, IC11 pin 8 to the low state. This will inhibit generation of SEL 0, SEL 1,
SEL 2 and SEL 3 allowing extra I/O to be interfaced.
The memory select lines may also be disabled by the use of a line present on the bus expansion socket.
MEMMAP EN HD5 pin 6C (see 045165 sheet 1). This line, when set low, puts S0 and S1 high which disables
the selection of ROMSEL 1, ROMSEL 2 and RAMSEL.