Johnson DM3474, Руководство по обслуживанию

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PROGRAMMING
3-7
Part No. 001-3474-002
3.4 TRANSMIT TO RECEIVE SEQUENCE
Refer to Figure 3-6.
1. 7.5 TX is turned OFF. For best TX adjacent channel power performance this could be shaped.
2. The synthesizer load process could begin slightly before, but when the last bit is strobed in the synthesizer it will
become unlocked. For ETSI specs, the TX should be turned OFF “on-frequency”.
3. The 5RCL line should switch from low to high AFTER the 7.5 TX is switched. The 5RCL not only turns the RX
circuits on but also Pin Shifts the VCO.
4. For quickest lock times the SYNTH ENABLE line on the last load word should be held high for 2 to 3 millisec-
onds. It MUST NOT be left high as the synthesizer in the SPEEDUP mode has poor noise performance and
would degrade the RX performance.
Figure 3-6 TX TO RX TIMING DIAGRAM
Speedup is 2 to 3 ms
Lock is approximately 7 ms
Ramp is approximately 3 ms
IMPORTANT
If the receiver is to be operated at 510-512 MHz (-810), a spurious condition may occur to degrade the
receiver sensitivity 2 to 3 dB. If this degradation is unacceptable, the synthesizer can be reprogrammed to a
comparison frequency (FCM) of 31.25 kHz (so that a multiple of this would not be 52.95 MHz) and a modulus
(FMOD) of 5 with a reference divide (NR) of 560. These parameters place the spurious at harmonics of 31.25 kHz
(instead of 50 kHz) outside the passband of the IF filters where the sensitivity is not degraded.