SX8 User Manual
G-‐UM-‐00004 Rev 006
20 of 45
•
Bit 7 (operation summary bit) is the summary bit for the operation
status register. It is set if any bit in the operation event register is
set while the corresponding bit in the operation event enable
register is set.
Service Request Enable Register
The service request enable register determines which summary bits in
the status byte register can generate service requests. If a summary bit
in the status register is set to 1 and the corresponding bit in the service
request enable register is set to 1, a service request is generated by the
switch. A new service request is not generated for this condition unless
the bit in the status register or the bit in the service request enable
register is cleared and the condition reoccurs.
Standard Event Status Register
•
Bit 0 (operation complete) is set in response to the
*OPC
common
command. This bit is set when all operations are complete.
•
Bit 1 (request control) is always set to 0.
•
Bit 2 (query error) is set when a query error occurs, for example, an
attempt is made to read the output queue when the output queue
is empty or when the data in the output queue is lost.
Service Request Enable Register
Read with
*SRE?
common query (the value of bit 6 is always 0)
Written to with
*SRE
common command (the value of bit 6 is always
zero, regardless of the value sent with the command)
Cleared by
*SRE
common command with a parameter value of 0
Power-‐on
Standard Event Status Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
power on
(PON)
user
request
(URQ)
command
error
(CME)
execution
error
(EXE)
device
dependent
error
(DDE)
query
error
(QYE)
request
control
(RQC)
operation
complete
(OPC)
Read with
*ESR?
common query
Written to with
Cannot be written to
Cleared by
*ESR?
common query
*CLS
common command
Power-‐on
