CMOS Setup Utility – Copyright © 1984 – 1998 Award Software
Advanced Chipset Features
SDRAM CAS Latency Time
3
SDRAM Cycle Time Tras/Trc
6/8
SDRAM RAS-to-CAS Delay
3
SDRAM RAS Precharge Time 3
System BIOS Cacheable Enabled
Video BIOS Cacheable
Enabled
Memory Hole At 15M-16M Disabled
Delay Transaction
Enabled
On-Chip Video Window Size
64MB
* Onboard Display Cache Setting *
CAS# Latency
3
Paging Mode Control
Closed
RAS-to-CAS Override
Closed
RAS# Timing
Slow
RAS# Precharge Timing Slow
Item Help
______________________
Menu Level
Move Enter: Select +/-/PU/PD: Value F10:Save ESC: Exit F1:General Help
F5:Previous Values F6:Optimal defaults F7:Standard Defaults
This section allows you to configure the system based on the specific features of the installed
chipset. This chipset manages bus speeds and access to system memory resources, such as
DRAM and the external cache. It also coordinates communications between the conventional
ISA bus and the PCI bus. It must be stated that these items should never need to be altered.
The default settings have been chosen because they provide the best operating conditions for
your system. The only time you might consider making any changes would be if you
discovered that data was being lost while using your system.
DRAM Settings:
The first chipset settings deal with CPU access to dynamic random
access memory (DRAM). The default timings have been carefully chosen and should only
be altered if data is being lost. Such a scenario might well occur if your system had mixed
speed DRAM chips installed so that greater delays may be required to preserve the
integrity of the data held in the slower memory chips.
SDRAM CAS Latency Time:
When synchronous DRAM is installed, the number of clock
cycles of CAS latency depends on the DRAM timing. You can select SDRAM CAS
(Column Address Strobe) latency according to your SDRAM specification
The Choice: 2, 3
SDRAM Cycle Time Tras/Trc:
Select the number of SCLKs for an access cycle.
The Choice:5/7,6/8.
SDRAM RAS-to-CAS Delay:
This field lets you insert a timing delay between the CAS and
RAS strobe signals, used when DRAM is written to, read from, or refreshed.
Fast
gives
faster performance; and
Slow
gives more stable performance. This field applies only when
synchronous DRAM is installed in the system.
The Choice: 2, 3.
SDRAM RAS Precharge Time:
If an insufficient number of cycles is allowed for the RAS
to accumulate its charge before DRAM refresh, the refresh may be incomplete and the
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