Janz Tec emPC-CX+, Справочное руководство системы

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emPC-CX+ ( System Reference Manual)

Appendices 4 - 39
Rev. 1.2
© Janz Tec AG
4.2 Personality Board Connector
In Table 13 the signal assignment of the personality board connector is shown for reference purposes.
1 GND GND 2
3 HDA_RST# HDA_SIN2 4
5 HDA_SDOUT HDA_SIN1 6
7 HDA_BITCLK HDA_SIN0 8
9 GND HDA_SYNC 10
11 GND GND 12
13 PCIE_TX5P PCIE_TX6P 14
15 PCIE_TX5N PCIE_TX6N 16
17 GND GND 18
19 PCIE_CLK6P PCIE_RX6N 20
21 PCIE_CLK6N PCIE_RX6P 22
23 GND GND 24
25 PCIE_CLK5P PCIE_RX5P 26
27 PCIE_CLK5N PCIE_RX5N 28
29 GND GND 30
31 CLKREQ5# CLKREQ6# 32
33 FPGA_IO_00 FPGA_IO_07 34
35 FPGA_IO_06 FPGA_IO_01 36
37 FPGA_IO_02 FPGA_IO_04 38
39 FPGA_IO_12 FPGA_IO_03 40
41 GND GND 42
43 FPGA_IO_08 FPGA_IO_05 44
45 FPGA_IO_10 FPGA_IO_11 46
47 FPGA_IO_13 FPGA_IO_15 48
49 FPGA_IO_17 FPGA_IO_09 50
51 FPGA_IO_14 FPGA_IO_16 52
53 GND GND 54
55 S_TXD2 +12V 56
57 S_DTR2 FPGA_IO_18 58
59 S_RTS2 FPGA_IO_19 50
61 S_RI2 FPGA_IO_20 62
63 S_RXD2 FPGA_IO_21 64
65 GND GND 66
67 S_DCD2 FPGA_IO_22 68
69 S_CTS2 FPGA_IO_23 70
71 S_DSR2 FPGA_IO_24 72
73 FPGA_SCL 74
75 FPGA_SDA 76
77 GND GND 78
79 CAN1_TX 80
81 CAN1_RX PCIE_RESET# 82
83 CAN1_TERM PCIE_WAKE# 84
85 CAN2_TX GND 86
87 CAN2_RX +5V0 88
89 CAN2_TERM +5V0 80
91 GND +3V3 92
93 GND +3V3 94
95 GND +3V3 96
97 +VCAN +3V3 98
99 GND GND 100
Table 13: Personality board connector pin assignment