Jäger ADwin-light-16, Руководство пользователя

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ADwin-light-16 , manual version 2.2, December 2004
A-5
Annex
ADwin
A-2 Hardware Addresses - General Overview
Address
[HEX]
Function Bit No. Comments
Register available
in the module
31...16 15...6 5 4 3 2 1 0 L16
L16 +
CO1
L16 +
DIO1
20 40 00 00
set multiplexer to input channel (ADC
01... ADC 15)
- - - - - n n n
"nnn" binary = 0...7 decimal,
selected channel = nnn*2 + 1
x x x
20 40 00 10
start conversion: ADC #1 - - - - - - - s
s = 0 : start conversion
s = 1 : no effect
x x x start conversion: all DACs synchro-
nously
- - - - - s - -
20 40 00 20
conversion status (EOC)
ADC #1
- - - - - - - e
e = 0 : end of conversion
e = 1 : conversion is running
x x x
20 40 00 30 read out register: ADC #1 - x x x x x x x x : result of conversion x x x
20 40 00 50 only write into register: DAC #1 - x x x x x x x
x : digital value to be converted x x x
20 40 00 60 only write into register: DAC #2 - x x x x x x x
20 40 00 B0
input register
DIGIN-05:00
- - x x x x x x x : read digital value x x x
20 40 00 C0
output register
DIGOUT-05:00
- - x x x x x x x : digital value to be output x x x
20 40 00 C4 set DIGOUT bits - - x x x x x x
x = 0 : no effect
x = 1 : set bit
x x x
20 40 00 C8 clear DIGOUT bits - - x x x x x x
x = 0 : no effect
x = 1 : clear bit
x x x
20 40 01 00
read out register and start conver-
sion: ADC #1
- x x x x x x x x : digital value to be converted x x x
20 40 02 00
write into register and start conver-
sion immediately: DAC #1
- x x x x x x x x : digital value to be converted x x x
20 40 02 04 contents of Latch A, counter #1 x x x x x x x x x : contents of latch register x x x
20 40 02 08
contents of Latch B, counter #1
(DIO1 only)
x x x x x x x x x :contents of latch register - - x
20 40 02 10
write into register and start conver-
sion immediately: DAC #2
- x x x x x x x x : digital value to be converted x x x
20 40 02 14 contents of Latch A, counter #2 x x x x x x x x x : contents of latch register x - x
20 40 02 18 contents of Latch B, counter #2 x x x x x x x x x : contents of latch register - - x
20 40 03 00
enable/disable counter:
CNT_ENABLE
()
- - - - - - x x
x = 0 : disable counter
x = 1 : enable counter
x
Bit 0
only
x
20 40 03 10 clear counter:
CNT_CLEAR
() * - - - - - - x x
x = 0 : no effect
x = 1 : clear counter
x
Bit 0
only
x
20 40 03 20 latch counter:
CNT_LATCH
() * - - - - - - x x
x = 0 : no effect
x = 1 : latch counter
x
Bit 0
only
x
20 40 03 30 counter inputs CLR or LATCH - - - - - - x x
x = 0 : CLR input
x = 1 : LATCH input
- - x
20 40 03 40
impulse/event counter or pulse
width/period duration measurement
- - - - - - x x
x = 0 :external clock input
x = 1 : internal reference clock
(20MHz / 5MHz)
- - x
20 40 03 50
4 edge evaluation/ CLK+DIR
or
20MHz / 5MHz reference clock
- - - - - - x x
CNT_MODE
=0:
x=0: 4 edge evaluation;
x=1: CLK+DIR
- - x
CNT_MODE
=1:
x=0: 20MHz;
x=1: 5MHz
20 40 04 54 bits DIO-15:00 - x x x x x x x
x = 0: clear output
x = 1: set output
- - x
20 40 04 64 bits DIO-31:16 - x x x x x x x
x = 0: clear output
x = 1: set output
- - x
20 40 04 74 set bits DIO-15:00 ** - x x x x x x x
x = 0: no effect
x = 1: set output
- - x
20 40 04 84 set bits DIO-31:16 ** - x x x x x x x
x = 0: no effect
x = 1: set output
- - x
20 40 04 94 clear bits DIO-15:00 ** - x x x x x x x
x = 0: no effect
x = 1: clear output
- - x
20 40 04 A4 clear bits DIO-31:16 ** - x x x x x x x
x = 0: no effect
x = 1: clear output
- - x
20 40 04 6C
configure inputs/outputs
CONF_DIO()
Bit 0: DIO 07:00; Bit 1: DIO 15:08
Bit 2: DIO 23:16; Bit 3: DIO 31:24
- - - - x x x x
x = 0: group as input
x = 1: group as output
- - x
* after execution the register is automatically reset
** function without any effect at inputs