DIO1 Add-On
ADwin
28
ADwin-light-16
, manual version 2.2, December 2004
8.2 Counters
Counter
The add-on DIO1 provides
two 32-bit counters
, which you can configure and
read out individually or all together. You can transfer single-ended or differen-
tial signals to the inputs.
The counters replace the incremental counters of the basic version.
Latch
The counters can be
internally or externally clocked
and are read out via
accompanying latches. All counters have a latch A as well as a latch B (the fig-
ure shows the design of a single counter).
The counter values can be cleared or transferred into a latch by using program-
ming instructions or (at special configurations) when there is an external signal
at CLR/LATCH.
There are the following operating modes: event counting (external clock) and
pulse width measurement (internal clock), see also chapter 8.2.2 / 8.2.3
:
External clocking
4.
Event counting:
Incrementing/decrementing of the counter is caused
by external square-wave signals at the inputs A/CLK and B/DIR. A sig-
nal at CLR/LATCH either sets the counter to zero (CLR) or has the
counter value written into the latch (LATCH).
There are the modes:
•
Clock and direction
: Every positive edge at CLK increments or
drecrements the counter value by one. The signal at DIR
determines the counting direction (0 = down, 1 = up).
•
Four edge evaluation
: Every edge of the signals (off-phase by
90 degrees) at A/CLK and B/DIR causes the counter to
increment/decrement. The counting direction is determined by
the sequence of the rising/falling edges of these signals. This
mode is particularly used for incremental encoders.
Internal clock
5.
Pulse width measurement:
Incrementing/decrementing of the counter
is caused by an internal reference clock with a signal frequency of
20 MHz (optionally 5 MHz after scaler). The square-wave signal at
CLR/LATCH is evaluated: With every positive edge of the input signal
the counter value is written to latch A, with a negative edge to latch B.
You can calculate:
• the period duration of the input signal at CLR/LATCH from the
values in latch A and latch B.
• the impulse width and pause time from the values in latch A and
latch B.
Fig. 25 – Block diagram of DIO1 counter
NOTE:
Only Counter #1 is shown for clarity of the schematic. The 20 MHz clock signal is distributed to second divider/counter.
G
20 MHz
Control-Registers
32 bit Latch B (#1, #2)
32 bit Counter (#1, #2)
32 bit Latch A (#1, #2)
CLK
EN
CLR
A / CLK
ADwi
n
-li
g
h
t-16
bus
Data
Data
Data
B / DIR
CLR /
LATCH
DIR
DIR
CNT_INPUTMODE
CNT_SET
(CNT_MODE)
CNT_CLEAR
CNT_LATCH
CNT_SET
(CNT_MODE)
CNT_MODE
Up
4-edge-
evaluation
ref.-CLK
4k7
4k7
4k7
to f
ref
-switch of
second counter
Divider
÷ 4
