IXYS CPC5622-EVAL-600R, Руководство пользователя

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NTEGRATED
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IRCUITS
D
IVISION
LITELINK III Evaluation Board Users Guide
2
www.ixysic.com
UG-CPC5622-EVAL-600R - Rev A
2. Setup and Using the Evaluation Board
This section describes setting up the CPC5622-EVAL-600R Evaluation Board prior to use.
2.1 Connections
The CPC5622-EVAL-600R evaluation board uses two
100 mil (2.54 mm) pitch pin headers, J1 and J2, for the
input and output connections. IXYS IC recommends
constructing header jumpers to bring the connections
out to your development or test platform. Connector
J1, the two-position pin header, provides access to the PSTN loop connections while J2, the 12-position pin
header, provides access for the low voltage side
power, logic control, logic-level loop status detector
outputs and the analog transmit and receive voice
paths.
NOTE: For clarity and consistency with the schematic, the schematic names will be used from this point forward
throughout the text.
Table 1: Telephone Network Access Connector - J1
Pin
Silk
Screen Schematic
Name
Use
1 1 RING Connect to the Ring (B) lead of the telephone network or a loop simulator.
2 TIP Connect to the Tip (A) lead of the telephone network or a loop simulator.
Table 2: Low Voltage Side Power and Signal Connector - J2
Pin
Silk
Screen Schematic
Name
Use
1 V+ VCC
Power input: +3.3 V
DC
or +5 V
DC
2 TX- TX-_IN Inverting analog input to the LITELINK
3 TX+ TX+_IN Non-inverting analog input to the LITELINK
4 RX- RX-_OUT Negative analog output from LITELINK
5 RX+ RX+_OUT Positive analog output from LITELINK
6 LOOP LOOP Loop Presence detector output
7 OH OH* Hook switch control. Off-Hook: OH* = 0, On-Hook: OH* = 1
8 RING2 RING2* F ull-wave ringing detector output
9 RING RING* H alf-wave ringing detector output
10 LIU LIU* Line In Use detector output
11 GND Low voltage side ground
12 POL POLARITY Polarity Detector output