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NTEGRATED
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IRCUITS
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IVISION
LITELINK III Evaluation Board Users Guide
4
www.ixysic.com
UG-CPC5622-EVAL-600R - Rev A
This evaluation board differs from previous generation
evaluation boards by incorporating a common mode
noise cancellation circuit that improves longitudinal
balance and common mode rejection across the voice
band spectrum. This is accomplished by using a small
capacitance from shapes on the printed circuit board
(PCB) and modifications to the recommended passive
components values that set the analog transmission
parameters. Details in the construction of the PCB
capacitor are provided in the evaluation board’s
printed circuit board design files available on line.
3.1 Connector J1 - Tip and Ring
Connector J1, the two-pin header, provides access to
the Tip and Ring (T/R) terminals of the evaluation
board. The Ring lead is located on pin 1 of the
connector and pin 2 is the Tip lead. Although the
board’s layout is designed for lightning and power
cross surge testing, the connector and it’s 25 mil
square pins are not rated for the peak voltages or
currents specified in the safety regulations. It is
suggested the connector be removed and lead wires
be soldered to the board when performing these tests.
3.2 Connector J2 - Low Voltage Side Interface
Providing access to the low voltage side analog and
digital interface is connector J2, a single row 12-pin
header connector with 25 mil square pins on 100 mil
centers. Due to space limitations, the silkscreen pin
names where modified slightly from the net names
shown on the schematic. These naming differences
are shown in
Table 1
and
Table 2 on Page 2
.
Pin 1: VCC
Power pin for the low voltage (SELV) side circuits.
Apply a nominal 3.3V
DC
or 5V
DC
with respect to the
ground (GND) connection at Pin 11.
Pin 2: TX-_IN
Pin 3: TX+_IN
Pins 2 and 3 are the analog voice negative (TX-) and
positive (TX+) differential inputs for the transmit path
(SELV to T/R). The maximum signal applied to these
input pins is 0dBm. (This is 0.548Vp on each input.)
For applications where the analog source is single
ended, short one of the input pins to ground and apply
the analog signal to the other input. Typically, TX- is
shorted to ground and the signal is applied to TX+. For
single ended applications, the maximum input signal is
still 0dBm. (This is 1.095Vp.)
Pin 4: RX-_OUT
Pin 5: RX+_OUT
Pins 4 and 5 are the analog voice negative (RX-) and
positive (RX+) differential outputs for the receive path
(T/R to SELV). The maximum output signal by these
pins is 0dBm. This is 0.548Vp on each output.
For single ended receive applications, connect one of
the output pins to the receiver input pin and leave the
other output open. This will result in a receive path
loss of 6dB.
Pin 6: LOOP
This is a logic level output indicating the presence of
loop battery feed from the network. For tip to ring
voltages greater than approxi/-5V
DC
the
detector will output a logic high (LOOP = 1) and for
T/R voltages less than approxi/-3V
DC
the
detector will output a logic low (LOOP = 0). The LOOP
detector is polarity insensitive.
Pin 7: OH*
OH* is an active low, TTL compatible, logic level input
used to control the hook switch function of the T/R
network interface. Applying a logic low (OH* = 0) at
this pin will enable the gyrator located on the line side
causing DC current to flow. This is commonly referred
to as the “Off-Hook” state. The gyrator, an electronic
inductor, has a low impedance at DC but a high
impedance in the voice band allowing the two-wire
interface to draw DC loop current without loading the
AC termination. An On-Hook state occurs when
OH* = 1 and loop current ceases.
The OH* net is connected to the OH input at pin 8 of
the CPC5622A. The CPC5622A requires this input to
be left open or pulled high to VCC during power up
and for a minimum duration of 50us following power
up. An internal pull-up resistor at the OH input
provides the required logic high when the input is left
open.