IWILL P6NS, Руководство пользователя

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When disa bled, the chipset beha ves a s if it were the ea rlier
This item a llows you to select between two methods of DRAM error checking,
ECC and Parity (default).
This item a llows you to select between three methods of memory error checking,
Auto, Ena bled a nd Disa bled
When a single bit error is detected, the offending DRAM row ID is la tched .
The la tched Va lued is held until softwa re explicit clea rs the error sta tus fla g.
You ca n select Ena bled or Disa bled.
This item determines the size of the L2 ca chea bility: 64MB / 512MB .
This item a llows you to select between two method of chipset NA# a sserted
during CPU write cycles /CPU line fills, Ena bled a nd Disa bled.
DRAM
ECC/PARITY
Select
Memory Parity /
ECC Check
Single Bit Error
Report
L2 Cache
Cacheable Size
Chipset NA#
Asserted
Pipeline Cache
Timing