IWILL P55TU, Руководство пользователя

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7/6 Seven clocks lea doff for rea ds a nd six clocks lea doff for writes.
6/5 Six clocks lea doff for rea ds a nd five clocks lea doff for writes.
7/6 Leadoff timing is the default.
When DRAM is refreshed, both rows a nd columns a re a ddressed sepa ra tely. This
setup item a llows you to determine the timing of the tra nsition from Row Address
Strobe (RAS) to Column Address Strobe (CAS).
3 Three CPU clock dela y.
2 Two CPU clock dela y.
3 CPU clocks is the default.
This sets the timing for burst mode rea ds from two different DRAM(EDO/FPM).
Burst rea d a nd write requests a re genera ted by the CPU in four sepa ra te pa rts.
The first pa rt provides the loca tion within the DRAM where the rea d or write is to
ta ke pla ce while the rema ining three pa rts provide the a ctua l da ta. The lower the
timing numbers, the fa ster the system will a ddress memory.
x222/x333 Rea d DRAM (EDO/FPM) timings a re 2-2-2/3-3-3
x333/x444 Rea d DRAM (EDO/FPM) timings a re 3-3-3/4-4-4
x444/x444 Rea d DRAM (EDO/FPM) timings a re 4-4-4/4-4-4
x222/x333 timings is the default.
This sets the timing for burst mode writes from DRAM. Burst rea d a nd write
requests a re genera ted by the CPU in four sepa ra te pa rts. The first pa rt provides
the loca tion within the DRAM where the rea d or write is to ta ke pla ce while the
Fast RAS# to
CAS# Delay
DRAM Read
<EDO/FPM>
DRAM Write Burst
Timing