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the input/output bus tha t the CPU must be dela yed to a llow for the completion of
the I/O.
This item a llows you to determine the recovery time a llowed for 8 bit I/O.
Choices a re from NA, 1 to 8 CPU clocks.
1 clock is the default.
This item a llows you to determine the recovery time
a llowed for 16 bit I/O. Choices a re from NA, 1 to 4 CPU clocks.
1 clock is the default.
In order to improve performa nce, certa in spa ce in memory ca n be reserved for
ISA ca rds. This memory must be ma pped into the memo ry spa ce below 16 MB.
Ena bled
Memory hole supported.
Disa bled
Memory hole not supported.
Disabled is the default.
Peer concurrency mea ns tha t more tha n one PCI device ca n be a ctive a t a time.
Ena bled
Multiple PCI devices ca n be a ctive.
Disa bled
Only one PCI device ca n be a ctive a t a time.
Enabled is the default.
When disa bled, the chipset beha ves a s if it were the
ea rlier
16 Bit I/O Recovery
Time
Memory Hole At
15M-16M
Peer Concurrency
Chipset Special
Features
Содержание P55TU
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