
REL0.1
Page 43 of 58
i.MX8 SMARC SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.10
i.MX8M PinMultiplexing on SMARC Edge
The i.MX8M CPU IO pins have many alternate functions and can be configured to any one of the alternate functions based on the requirement, also most of
the i.MX8M
CPU’s IO pins can be configured as GPIO if required. The below table provides the details of
i.MX8M CPU pin connections to the SMARC edge
connector and with selected pin function highlighted and available alternate functions. This table has been prepared by refer
ring NXP’s
i.MX8M Hardware
User’s Manual.
Important Note: It is strongly recommended to use the pin function same as selected in the SMARC
SOM Edge connector for iWave’s BSP reusability and to
have compatible SMARC modules in future for upgradability.
Table 8: i.MX8M CPU IOMUX for SMARC Edge Connector interfaces
Interface/
Function
SMARC
Edge
Pin
Number
i.MX8M
CPU
Pin
Number
Function 0
Function 1
Function 2
Function 3
Function 4
Function 5
GPIO
Default
State
MIPI CSI0
S9
B22
MIPI_CSI1_CLK_N
MIPI_CSI1_CLK_N
S8
A22
MIPI_CSI1_CLK_P
MIPI_CSI1_CLK_P
S12
B23
MIPI_CSI1_D0_N
MIPI_CSI1_D0_N
S11
A23
MIPI_CSI1_D0_P
MIPI_CSI1_D0_P
S15
D22
MIPI_CSI1_D1_N
MIPI_CSI1_D1_N
S14
C22
MIPI_CSI1_D1_P
MIPI_CSI1_D1_P
S6
H5
sai1.MCLK
sai5.MCLK
sai1.TX_BCLK
gpio4.IO[20]
gpio4.IO[20]
sai1.MCLK
S5
G8
i2c3.SCL
pwm4.OUT
gpt2.CLK
gpio5.IO[18]
gpio5.IO[18]
i2c3.SCL
S7
E9
i2c3.SDA
pwm3.OUT
gpt3.CLK
gpio5.IO[19]
gpio5.IO[19]
i2c3.SDA
MIPI CSI1
P4
B19
MIPI_CSI2_CLK_N
MIPI_CSI2_CLK_N
P3
A19
MIPI_CSI2_CLK_P
MIPI_CSI2_CLK_P
P8
D20
MIPI_CSI2_D0_N
MIPI_CSI2_D0_N
P7
C20
MIPI_CSI2_D0_P
MIPI_CSI2_D0_P
P11
B20
MIPI_CSI2_D1_N
MIPI_CSI2_D1_N
P10
A20
MIPI_CSI2_D1_P
MIPI_CSI2_D1_P
P14
B21
MIPI_CSI2_D2_N
MIPI_CSI2_D2_N
P13
A21
MIPI_CSI2_D2_P
MIPI_CSI2_D2_P
P17
D19
MIPI_CSI2_D3_N
MIPI_CSI2_D3_N
P16
C19
MIPI_CSI2_D3_P
MIPI_CSI2_D3_P