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REL0.2
Page 39 of 58
i.MX8M SMARC SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Exp.
Pin No
Signal Name
CPU Ball Name/
Pin Number
Signal Type/
Termination
Description
53 SAI1_RXD6 SAI1_RXD6/
G2 I, 1.8V CMOS/
10K PD SAI1 Receiver Data 6.
45 SAI1_RXD7 SAI1_RXD7/
G1 I, 1.8V CMOS/
10K PD SAI1 Receiver Data 7.
49 SAI1_RXFS SAI1_RXFS/
L1 I, 1.8V CMOS SAI1 Receiver Frame Sync Output.
55 SAI1_RXC SAI1_RXC/
K1 I, 1.8V CMOS SAI1 Receiver Clock Input.
2.8.2 MIPI CSI Camera Interface
The I.MX8M processor supports two four lane MIPI CSI camera interface whereas SMARAC edge connector support
one two lane and one four lane MIPI CSI, hence data2 and data3 lane of CSI0 channel are connected to board expansion
connector.
For more details on MIPI CSI expansion signals, refer below table:
Exp.
Pin No
Signal Name
CPU Ball Name/
Pin Number
Signal Type/
Termination
Description
80 MIPI_CSI1_D2_P MIPI_CSI1_D2_P/
C23 I, MIPI MIPI CSI0 differential data lane 2
positive.
82 MIPI_CSI1_D2_N MIPI_CSI1_D2_N/
B24 I, MIPI MIPI CSI0 differential data lane 2
negative.
86 MIPI_CSI1_D3_P MIPI_CSI1_D3_P/
D21 I, MIPI MIPI CS0 differential data lane 3
positive.
88 MIPI_CSI1_D3_N MIPI_CSI1_D3_N/
C21 I, MIPI MIPI CSI0 differential data lane 3
negative.
2.8.3 GPIOs
Refer GPIO Column under “ i.MX8M Pin Multiplexing on Expansion Connector ” for details on GPIO options available
from Expansion connector.