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RZ/G1H Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.8.5 SPI Interface
The RZ/G1H Qseven SOM supports one SPI interface on Expansion connector2. RZ/G1H CPU’s MSIOF3 is used for SPI
interface which supports full-duplex synchronous four-wire serial interface with DMA.
The RZ/G1H CPU’s MSIOF3 supports serial formats IIS, SPI (master and slave modes) at max speed of 26Mbps. It
supports 32bit x 64 stages for transmit FIFOs & 32bit × 256 stages for receive FIFOs and allows MSB first or LSB first
selectable for data transmission and reception.
For more details, refer Expansion connector2 pins 61, 63, 65, 67 & 69 on Table 8.
2.8.6 PWM Interface
The RZ/G1H Qseven SOM supports three PWM interface on Expansion Connector2. RZ/G1H CPU’s PWM 0, PWM3 and
PWM4 channels are used for PWM interface. This PWM timer has a 10-bit counter and supports configurable PWM
output cycle within the range from 2 cycles to 224 × 1024 cycles of internal bus clock (i.e. from 30.77 ns to 264 seconds
when bus clock = 65 MHz). Also, it supports continuous pulse output mode or single pulse output mode.
For more details, refer Expansion connector2 pin 13, 39 & 58 on Table 8.
Note: In RZ/G1H Qseven SOM, three TPU0 signals (TPU0TO0, TPU0TO1 & TPU0TO2 channels) which are connected to
Qseven Edge connector is also connected to Expansion connector2. Please refer Expansion connector2 pin 29, 36 & 37
on Table 8