IOtech DaqBoard/500, Справочник по аппаратуре

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Clocks, Triggers, Counters, and Timers
ADCLKIN – Uses pin #2 or pin #5. ADCLKIN is the ADC External Pacer Clock Input. This input
recognizes TTL level signals and is edge sensitive. The active edge is selectable as either rising or falling.
The ADCLKIN signal connection can be made at either pin #2 or pin #5,
but NOT both at the same time.
ADCLKOUT/TMR1 – Uses pin #37 for one of the following two functions.
ADCLKOUT is the ADC’s External Clock Output. Each time the ADC is clocked from any of the
available clocking sources the ADCLKOUT signal pulses high for a period of 1micro-second. This output
can be used to synchronize multiple A/D converters on different PCI cards allowing simultaneous A/D
conversions by connecting the ADCLKOUT to the ADCLKIN input of each PCI card.
TMR1 is an LSTTL output signal that provides a second clock source with characteristics identical to
TIMER0. The connection makes use of a separate [and independent] TMR1 internal software pacer clock.
The ADCLKOUT signal line is shared with the on-board TMR1 Clock Output signal, pin #37
on the 68-pin SCSCI III connector. Only one output signal may be generated to the ADCLKOUT
/ TMR1 pin (or associated terminal) at any given time. TIMER 1 is automatically disabled in
hardware when the ADCLKOUT is enabled.
ADTRGIN – Uses pin #6. ADTRGIN is the External ADC Trigger/Gate Input. This input recognizes
TTL level signals and is used to start or stop the ADC acquisition process. The input is selectable as either
rising/falling edge or active high/low level sensitivity
.
ADTRGOUT/TMR0 – Uses pin #3 for one of the following two functions.
ADTRGOUT is the internal ADC’s Trigger Output. Each time the ADC is triggered from any of the
available triggering sources the ADTRGOUT signal pulses high for a period of 1 µs. This output can be
used to synchronize multiple A/D converters on different cards allowing simultaneous A/D triggering by
connecting the ADTRGOUT to the ADTRGIN input of each PCI card.
The TMR0 LSTTL output signal provides a 50% duty cycle square wave derived from an independent
TMR0 internal software pacer clock. The pacer clock period can be set from 1 us to 65535 us, producing
an output clock rate from 500 KHz down to approximately 7.6295 Hz.
The ADTRGOUT signal line is shared with the on-board TIMER 0 Clock Output signal
(TMR0) pin #3 on the 68-pin SCSI III connector. Therefore only one output signal may be
generated to the ADTRGOUT / TMR0 terminal at any given time. The TIMER 0 is
automatically disabled in hardware when the ADTRGOUT is enabled.
2-4 Connections & Pinouts
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DaqBoard/500 Series User’s Manual