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ICM-30630

Page 8 of 18

Document Number: AN-000023
Revision: 1.1

Figure 5. Internal Power Supply for VDD1P2

3.2

PROGRAM/DEBUG INTERFACE AND EXTERNAL RESET

The RESET signal can be controlled via a host (active low), or can be left pulled high, and the internal POR will provide
the reset. For sensor HUB application, we recommend host control the reset. In addition to the hardware RESET input, a
soft reset can be provided by the host via a serial interface register write.

There are two ways to program the ICM-30630’s internal flash memory:



Via the SPI / I2C host interface: The host AP or a SPI Host Controller tool, such as Total Phase’s Cheetah system,
can be used to program ICM-30630 FLASH. InvenSense will provide Android/Linux supported FLASH
programming execution software.



When using the Cheetah tool to program FLASH, a digital signal level shifter is required for VDDIO, as the digital
supply voltage level is not the same as Cheetah’s I/O level (3.3V). Figure 6 shows the suggested level shifter
circuit incorporated in the ICM-30630 SDK board.

Figure 6. Programming the ICM-30630 Flash Memory through a Total Phase Cheetah System With a Level Shifter

I2C(M)

SPI/I2C(S)

GPIOs

CLOCK

PROGRAMMING

DEBUGGING

PWRs

ICM-30630

RESETL

RESV

SWDP1(DATA)

SWDP0(CLK)

AUX_CL

VDDIO

SDO/AD0

REGOUT

FSY NC/GPIO1

GPIO2

VDD

RESV

VDD1P2

XTALO

XTALI

GND

GPIO0

RESV

AUX_DA

nCS

SCL/SCLK

SDA/SDI

0.1uF

GND

VDDIO

VDD

RESETL-H

SDI-H

VDDIO

SDO-H

nCS-H

SCLK-H

RESETL-H

VDDIO

SDI

SCLK

SDI-H

nCS-H

SDO

nCS

SDO-H

MAX3378EEUD

IO-VL1

IO-VL2

IO-VL3

IO-VL4

GND

/Tri-State

IO-VCC4

IO-VCC3

IO-VCC2

IO-VCC1

VCC

C26

0.1uF

C27

0.1uF

MAX3378EEUD

IO-VL1

IO-VL2

IO-VL3

IO-VL4

GND

/Tri-State

IO-VCC4

IO-VCC3

IO-VCC2

IO-VCC1

VCC

C28

0.1uF

C29

0.1uF

HDR 5X2 2.54mmx2.54mm

CN2

SS2

SS3

MISO

SCLK

SS1

GND

MOSI

GND

3V3

GND

Cheetah Host CNN

GND

VDDIO

I2C(M)

SPI/I2C(S)

GPIOs

CLOCK

PROGRAMMING

DEBUGGING

PWRs

ICM-30630

RESETL

RESV

SWDP1(DATA)

SWDP0(CLK)

AUX_CL

VDDIO

SDO/AD0

REGOUT

FSY NC/GPIO1

GPIO2

VDD

RESV

VDD1P2

XTALO

XTALI

GND

GPIO0

RESV

AUX_DA

nCS

SCL/SCLK

SDA/SDI

RESETL

GND

VDDIO

Содержание ICM-30630

Страница 1: ...es the right to changespecifications and information herein without notice InvenSense Inc 1745 Technology Drive San Jose CA 95110 U S A 1 408 988 7339 www invensense com Document Number AN 000023 Revision 1 1 Revision Date 05 07 2015 ICM 30630 System Hardware Design Guide Revision 1 1 ...

Страница 2: ...M DEBUG INTERFACE AND EXTERNAL RESET 8 3 3 CLOCK GENERATION UNIT AND EXTERNAL CLOCK SOURCE 9 3 4 SERIAL INTERFACE DIGITAL LINE TERMINATIONS 11 3 4 1 SLAVE I 2 C INTERFACE 11 3 4 2 SLAVE SPI INTERFACE 12 3 4 3 MASTER I 2 C INTERFACE 12 3 5 GPIO LINES 13 4 PCB DESIGN GUIDELINES 14 4 1 EXTERNAL CRYSTAL 14 4 2 I 2 C AND SPI LINES 14 4 3 POWER AND GND 14 4 4 MEMS COMPONENT PLACEMENT 14 5 REFERENCE DESI...

Страница 3: ... Figure 6 Programming the ICM 30630 Flash Memory through a Total Phase Cheetah System With a Level Shifter 8 Figure 7 SWD Programming Debugging Interface Connection 9 Figure 8 External Crystal Oscillator Circuit 10 Figure 9 ICM 30630 Operating in Slave I 2 C Mode 11 Figure 10 ICM 30630 Operating in Slave SPI Mode 12 Figure 11 ICM 30630 Master I 2 C Bus Connection 12 Figure 12 ICM 30630 Reference D...

Страница 4: ...g features ARM Cortex M0 based open platform optimized for motion applications with dual DMP based motion accelerators Supports Android L and beyond Memory DMP FIFO variable size FIFO based on DMP feature set Runtime Calibration The ICM 30630 serves as a sensor hub supporting the collection and processing of data from internal and external sensors It can offload data processing from the Applicatio...

Страница 5: ... X GYRO ADC Y GYRO ADC Z GYRO TEMP SENSOR ADC ADC FIFO SRAM FLASH 64 KB USER CONFIG REGISTERS SENSOR REGISTERS ROM 32KB INTERRUPT STATUS REGISTERS COUNTERS TIMERS SELF TEST CHARGE PUMP MASTER I2C SERIAL INTERFACE MUX SERIAL WIRE DATA PORT OSC BIAS LDOs SLAVE I2C AND SPI SERIAL INTERFACE GPIO 3X DMP4 DMP3 ARM CORTEX M0 nCS SDA SDI AD0 SDO SCL SCLK AUX_CL AUX_DA SIGNAL CONDITIONING GPIO INT SWDIO SW...

Страница 6: ...lligent sensor hub that allows the data collection and processing of such data from internal and external sensors The multi cores of ICM 30630 are designed to offload computing and processing tasks from the AP thereby saving system power and streamlining the overall performance The device also integrates industry leading InvenSense 6 axis Accel and Gyro MEMS Figure 3 Sensor HUB Solution with ICM 3...

Страница 7: ...or decoupling purposes Proper capacitor decoupling can reduce power supply noise as capacitors act as a supplementing current source during short transient events InvenSense recommends using separate 0 1 µF decoupling capacitors for VDD VDDIO and REGOUT If using external 1 2 V supply a 0 1 µF decoupling capacitor is also needed All decoupling capacitors must be placed as close as possible to their...

Страница 8: ... 30630 Flash Memory through a Total Phase Cheetah System With a Level Shifter I2C M SPI I2C S GPIOs CLOCK PROGRAMMING DEBUGGING PWRs U1 ICM 30630 RESETL 1 RESV 2 RESV 3 RESV 4 SWDP1 DATA 5 SWDP0 CLK 6 AUX_CL 7 VDDIO 8 SDO AD0 9 REGOUT 10 FSYNC GPIO1 11 GPIO2 12 VDD 13 RESV 14 VDD1P2 15 XTALO 16 XTALI 17 GND 18 GPIO0 19 RESV 20 AUX_DA 21 nCS 22 SCL SCLK 23 SDA SDI 24 0 1uF C1 0 1uF C2 0 1uF C4 GND ...

Страница 9: ...ause they are built in ICM 30630 4 CMOS external 32 768 KHz clock For the ICM 30630 it is recommended to utilize precise external oscillators or crystals ceramic resonators The accuracy of an external oscillator or crystals ceramic resonator must be 30 ppm or better An external digital level clock input from a 32 768 kHz source often found on PMICs and other platform devices can be connected to XT...

Страница 10: ...it I2C M SPI I2C S PWRs CLOCK PROGRAMMING DEBUGGING U1 ICM 30630 RESETL 1 RESV 2 RESV 3 RESV 4 SWDP1 DATA 5 SWDP0 CLK 6 AUX_CL 7 VDDIO 8 SDO AD0 9 REGOUT 10 FSYNC GPIO1 11 GPIO2 12 VDD 13 RESV 14 VDD1P2 15 XTALO 16 XTALI 17 GND 18 GPIO0 19 RESV 20 AUX_DA 21 nCS 22 SCL SCLK 23 SDA SDI 24 AH 32 768KDZF T X1 ...

Страница 11: ...in slave I 2 C mode Pin 22 nCS must be set to the same level as VDDIO Figure 9 shows the ICM 30630 operating in slave I 2 C mode with its 7 bit device address set to 0x6A The I 2 C open drain pullup resister value can be adjusted based on how many slave devices are connected and the bus speed The 10K ohm in the below circuit is just for reference When the bus in fast and fast plus mode please refe...

Страница 12: ...below circuit is just for reference When the bus is in fast and fast plus mode please reference the Table 1 for the pullup resistors value Figure 11 ICM 30630 Master I 2 C Bus Connection SCLK From Application Processor CS MOSI MISO I2C M SPI I2C S GPIOs CLOCK PROGRAMMING DEBUGGING PWRs U1 ICM 30630 RESETL 1 RESV 2 RESV 3 RESV 4 SWDP1 DATA 5 SWDP0 CLK 6 AUX_CL 7 VDDIO 8 SDO AD0 9 REGOUT 10 FSYNC GP...

Страница 13: ...re referenced to VDDIO We recommend the following GPIO usage assignment a Use ICM 30630 GPIO0 as output to wakeup host MCU Connect the GPIO0 to host MCU wake up interrupt input b Use ICM 30630 GPIO1 as output for general non wakeup interrupt of host MCU Connect the GPIO1 to host MCU interrupt input c ICM 30630 GPIO2 is used as a sensor interrupt input or GPIO d Host wakes up ICM 30630 with an inte...

Страница 14: ...igh speed digital bus all I 2 C and SPI data and clock lines should be length and impedance matched Keep the bus traces as short as possible to reduce bus capacitance Avoid routing high energy traces near digital bus lines 4 3 POWER AND GND Although the ICM 30630 is low power component wider power and ground PCB traces are very helpful to reduce system noise It is recommended to design power and g...

Страница 15: ...M_0R R46 NM_0R R42 CN12 HDR 5X2 2 54mmX2 54mm 2 4 6 8 10 1 3 5 7 9 0R R7 USB mini ty pe B CN2 GND 5 ID 4 DP 3 VBUS 1 DM 2 NC3 6 NC4 7 NC2 8 NC1 9 D1 LED0402_RED 1 2 U9 SN74LVC1G11DBVR A 1 GND 2 B 3 Y 4 VCC 5 C 6 R31 10K SOT235 TLV70233DBVR U5 Vin 1 OUT 5 GND 2 EN 3 NC 4 NM_0R R40 R19 10K SIP 3 2 54mm JP2 1 2 3 3V3 GND GND GND VDD VIN GND VIN GND GND VDDIO GND GND VIN GND GND GND VIN GND GND VDD SW...

Страница 16: ... 9 1 D1 LED0402_RED Kingbright Corp APHHS1005SURCK LED0402 10 2 JP1 JP2 SIP 3 2 54mm FCI 68000 103HLF sip 3p 11 1 JP3 2X1 HEADER Samtec TS 102 T A sip 2p 12 1 LED1 LED0402_GRN Kingbright Corp APHHS1005CGCK LED0402 13 6 R3 R4 R19 R24 R30 R31 10K Yageo RC0402JR 0710KL R0402 14 1 R4 510R Vishay CRCW0402510RFKED R0402 15 8 R5 R6 R7 R8 R10 R11 R48 R49 0R Panasonic ERJ 2GE0R00X R0402 16 1 R26 1K Panason...

Страница 17: ... Number AN 000023 Revision 1 1 REVISION HISTORY REVISION DATE REVISION DESCRIPTION 11 21 2014 1 0 Initial Release 05 07 2015 1 1 Added SWDP0 operation and programming debugging modes selections Removed external crystal load capacitors ...

Страница 18: ... information contained in this document or from the use of products and services detailed therein This includes but is not limited to claims or damages based on the infringement of patents copyrights mask work and or other intellectual property rights Certain intellectual property owned by InvenSense and described in this document is patent protected No license is granted by implication or otherwi...

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