ICM-30630
Page 9 of 18
Document Number: AN-000023
Revision: 1.1
ICM-30630’s FLASH can also be programmed through the SWD interface by utilizing SWDCLK and SWDIO signal
lines. The same serial-wire debug interface also serves as debug interface port.
SWDP0 (pin-6) must be connected to GND in normal operation mode. When in debug/program mode, do not
connect the SWDP0 (pin-6) to GND.
Figure 7. SWD Programming/Debugging Interface Connection
3.3
CLOCK GENERATION UNIT AND EXTERNAL CLOCK SOURCE
The ICM-30630 offers three different clock sources:
1.
Built-in high-frequency RC oscillator for the system clock
2.
Built-in low-frequency RC oscillator for periodic wake up
3.
External 32.768 kHz crystal for accurate time stamping.
An external crystal is connected to XTALI and XTALO (Pins 17 and 18).
There is no need to mount crystal load
capacitors on PCB board because they are built in ICM-30630.
4.
CMOS external 32.768 KHz clock.
For the ICM-30630, it is recommended to utilize precise external oscillators or crystals/ceramic resonators. The accuracy of
an external oscillator or crystals/ceramic resonator must be 30 ppm or better.
An external digital level clock input from a 32.768 kHz source often found on PMICs and other platform devices can be
connected to XTALI pin. We recommend this methodology as it allows ICM-30630 to be synchronized with other devices
(i.e. the host) who are also using the same reference clock.
VDDIO
VDDIO
GND
SWDIO
RESETL
R30
10K
FTSH-105-01-L-DV-K-A-P
CN7
1
3
5
7
9
2
4
6
8
10
J1
2X1 HEADER
1
2
GND
SWDCLK
SWDCLK
For normal operation, short J1 pin1-2
For programming and debugging, open J1 pin1-2
I2C(M)
SPI/I2C(S)
PWRs
CLOCK
PROGRAMMING
DEBUGGING
U1
ICM-30630
RESETL
1
RESV
2
RESV
3
RESV
4
SWDP1(DATA)
5
SWDP0(CLK)
6
AUX_CL
7
VDDIO
8
SDO/AD0
9
REGOUT
10
FSY NC/GPIO1
11
GPIO2
12
VDD
13
RESV
14
VDD1P2
15
XTALO
16
XTALI
17
GND
18
GPIO0
19
RESV
20
AUX_DA
21
nCS
22
SCL/SCLK
23
SDA/SDI
24
