ZL2005PEV4
6
ZL2005PEV4DSr1.0
Figure 4. ZL2005P Interface
C6
8
22uF
SD
A
R1
7
19.
6k
R1
8
21.
5k
R1
9
23.
7k
R2
0
26.
1k
R2
1
28.
7k
VI
1
G
2
VO
3
G
4
U1
0
M
IC
2920A-3.
3
BS
J1
C
O
N
2
_
B
anana
Place pullup
s
near J11
D1
2
BAT
5
4
T
o
Next
Rail
F
rom Pre
vious
Rail
SY
N
C
EN
_BU
S
+V
i2
c
D1
1
GR
N
Q1
0
2N
7002/
SOT
R1
4
470
SALR
T
B
ackside
+V
i2
c
EN
_BU
S
PG
En
a
b
le
o
n
PG
_
0
E
n
abl
e
O
p
en
E
n
abl
e
on
B
u
s
PG_0
SC
L
En
a
b
le
Mo
n
ito
r
D
is
abl
e
T
h
e
r
e
fe
renc
e
des
igns
c
ont
ai
ned
in
t
h
is
doc
um
e
n
t
are
f
o
r
ref
e
renc
e an
d ex
am
p
le
pur
pos
e
onl
y
.
T
H
E R
E
F
E
R
E
N
C
E
D
ESI
G
N
S AR
E
PR
OVI
D
ED
"
AS
IS
" AN
D
"
W
IT
H
ALL F
A
U
L
T
S
" AN
D
Z
ILKER
LABS
D
ISC
LAM
ES ALL
W
A
R
R
AN
T
IES,
W
H
ET
H
E
R
D
IR
E
C
T
, I
N
D
IR
E
C
T
,
C
O
N
SEQU
E
N
T
IA
L
(I
NCL
UDI
NG
L
O
S
S
O
F
P
R
O
F
IT
S
),
O
R
O
T
HE
RW
IS
E
, R
E
S
U
L
T
ING
FRO
M
T
H
E
R
E
FE
RE
NCE
D
ESI
GN
S O
R
AN
Y
U
SE
T
H
ER
EOF
.
Any
us
e of
s
u
c
h
re
fe
re
nc
e des
igns
i
s
at
y
o
u
r ow
n
ri
s
k
a
nd
y
o
u
agr
ee t
o
i
ndem
ni
fy
Z
ilk
er
Lab
s
fo
r
any
d
a
m
a
ges
res
u
lt
in
g
f
rom
s
u
c
h
u
s
e.
Ti
tl
e
Siz
e
D
o
c
u
m
ent
N
u
m
ber
R
e
v
Sheet
of
4301 W
EST
B
A
N
K
D
R
IV
E
BU
IL
D
IN
G
A,
SU
IT
E 100
AU
ST
IN
, T
E
X
AS 78746
Z
IL
K
E
R
L
A
BS
, I
N
C
. C
O
N
F
ID
EN
T
IAL
AN
D
P
R
O
P
R
IE
T
A
R
Y
R
S
C
H
-Z
L
2
005-
0
1
6
2
S
C
HE
M
A
T
IC,
I
n
te
rf
a
c
e
A
22
T
ues
da
y
, J
une 12,
200
7
R1
5
10.
0K
R1
1
10.
0K
PG
VO
U
T
2
4
6
8
10
1
3
5
7
9
J1
0
H
EAD
ER
5X
2
1
2
3
SW
1
SW
_SPD
T
C6
7
22u
F
D1
0
ST
PS20L45
C
G
D
-2PAK
C6
3
1
80uF
16
V
R1
3
10.
0K
R1
0
10.
0K
2
4
6
8
10
1
3
5
7
9
J1
1
H
EAD
ER
5X
2
R1
2
10.
0K
+V
i2
c
VI
N
+V
i2
c
SALR
T
SD
A
SC
L
VT
R
K
SY
N
C
EN
SA0
2
1
3
4
JP
1
Th
is reg
ulator
allow
s stand
alone
opera
tion w
hen no
t
us
ing a
USB do
ngle.
When n
o
USB
dongle
is ap
plied,
th
is reg
ualtor
is su
pplying
Vi2c
curren
t thus
ef
ficien
cy mea
sureme
nts wil
l be a
ffecte
d.
Addr
0x
20
0x
21
0x
22
0x
23
0x
24
2
1
3
4
5
6
7
8
9
10
J1
2
H
EAD
ER
5x
2
PI
N
VI
N
Содержание ZL2005P
Страница 7: ...ZL2005PEV4 ZL2005PEV4DSr1 0 7 Board Layout Figure 5 PCB Silk Screen Top ...
Страница 8: ...ZL2005PEV4 8 ZL2005PEV4DSr1 0 Figure 6 PCB Top Layer ...
Страница 9: ...ZL2005PEV4 ZL2005PEV4DSr1 0 9 Figure 7 PCB Inner Layer 1 ...
Страница 10: ...ZL2005PEV4 10 ZL2005PEV4DSr1 0 Figure 8 PCB Inner Layer 2 ...
Страница 11: ...ZL2005PEV4 ZL2005PEV4DSr1 0 11 Figure 9 PCB Bottom Layer Top view ...
Страница 12: ...ZL2005PEV4 12 ZL2005PEV4DSr1 0 Figure 10 PCB Silk Screen Bottom Top View reversed ...