ZL2005PEV4
18
ZL2005PEV4DSr1.0
Test 3: Dynamic Load Response
For the dynamic load response test, the circuit was set to a nominal output voltage of 2.5 V and an input
voltage of 6 V. A 7.5 A to 10 A load step (rate of 2.5 A/µs) was applied and then released, and the
deviation from nominal output was captured in the charts below.
Transient L to H
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.0E+00
5.0E-05
1.0E-04
1.5E-04
2.0E-04
2.5E-04
3.0E-04
3.5E-04
4.0E-04
Time in Sec
V
o
u
t in
V
o
lt
Dynamic Load Response (Volts)
Figure 15. Dynamic Load Test Results
Transient H to L
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.0E+00
5.0E-05
1.0E-04
1.5E-04
2.0E-04
2.5E-04
3.0E-04
3.5E-04
4.0E-04
Time in Sec
V
o
u
t in
V
o
lt
VOUT in V
Figure 16. Dynamic Unload Test Results
Содержание ZL2005P
Страница 7: ...ZL2005PEV4 ZL2005PEV4DSr1 0 7 Board Layout Figure 5 PCB Silk Screen Top ...
Страница 8: ...ZL2005PEV4 8 ZL2005PEV4DSr1 0 Figure 6 PCB Top Layer ...
Страница 9: ...ZL2005PEV4 ZL2005PEV4DSr1 0 9 Figure 7 PCB Inner Layer 1 ...
Страница 10: ...ZL2005PEV4 10 ZL2005PEV4DSr1 0 Figure 8 PCB Inner Layer 2 ...
Страница 11: ...ZL2005PEV4 ZL2005PEV4DSr1 0 11 Figure 9 PCB Bottom Layer Top view ...
Страница 12: ...ZL2005PEV4 12 ZL2005PEV4DSr1 0 Figure 10 PCB Silk Screen Bottom Top View reversed ...