Reference Number: 327043-001
87
Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
• Definition:
Counts the number of cycles when the system is increasing voltage. There is no filter-
ing supported with this event. One can use it as a simple event, or use it conjunction with the occu-
pancy events to monitor the number of cores or threads that were impacted by the transition.
VR_HOT_CYCLES
• Title:
VR Hot
• Category:
VR_HOT Events
• Event Code:
0x32
• Max. Inc/Cyc:
1,
Register Restrictions:
0-3
• Definition:
2.7
Intel® QPI Link Layer Performance Monitoring
2.7.1
Overview of the Intel® QPI Box
The Intel® QPI Link Layer is responsible for packetizing requests from the caching agent on the way
out to the system interface. As such, it shares responsibility with the CBo(s) as the Intel QPI caching
agent(s). It is responsible for converting CBo requests to Intel QPI messages (i.e. snoop generation
and data response messages from the snoop response) as well as converting/forwarding ring
messages to Intel QPI packets and vice versa.
The Intel® QPI is split into two separate layers. The Intel® QPI LL (link layer) is responsible for
generating, transmitting, and receiving packets with the Intel® QPI link.
R3QPI (
Section 2.9, “R3QPI Performance Monitoring”
) provides the interface to the Ring for the Link
Layer. It is also the point where VNA/VN0 link credits are acquired.
In each Intel Xeon processor E5-2600, there are two Intel® QPI agents that share a single ring stop.
These links can be connected to a single destination (such as in DP), but also can be connected to two
separate destinations (4s Ring or sDP). Therefore, it will be necessary to count Intel® QPI statistics
for each agent seperately.
The Intel® QPI Link Layer processes two flits per cycle in each direction. In order to accommodate
this, many of the events in the Link Layer can increment by 0, 1, or 2 in each cycle. It is not possible
to monitor Rx (received) and Tx (transmitted) flit information at the same time on the same counter.
2.7.2
Intel® QPI Performance Monitoring Overview
Each Intel® QPI Port in the uncore supports event monitoring through four 48b wide counters
(Q_Py_PCI_PMON_CTR/CTL{3:0}). Each of these four counters can be programmed to count any
Intel® QPI event. The Intel® QPI counters can increment by a maximum of 6b per cycle (???).
Each Intel® QPI Port also includes a mask/match register that allows a user to match packets,
according to various standard packet fields such as message class, opcode, etc, as they leave the
Intel® QPI Port.
For information on how to setup a monitoring session, refer to
Section 2.1, “Uncore Per-Socket
Performance Monitoring Control”
.
