Reference Number: 327043-001
17
Intel® Xeon® Processor E5-2600 Product Family Uncore Performance Monitoring
2
Intel® Xeon® Processor E5-
2600 Product Family Uncore
Performance Monitoring
2.1
Uncore Per-Socket Performance Monitoring
Control
The uncore PMON does not support interrupt based sampling. To manage the large number of counter
registers distributed across many units and collect event data efficiently, this section describes the
hierarchical technique to start/stop/restart event counting that a software agent may need to perform
during a monitoring session.
2.1.1
Setting up a Monitoring Session
On HW reset, all the counters are disabled. Enabling is hierarchical. So the following steps, which
include programming the event control registers and enabling the counters to begin collecting events,
must be taken to set up a monitoring session.
covers the steps to stop/re-start counter
registers during a monitoring session.
For each box in which events will be measured:
Skip (a) and (b) for U-Box monitoring.
a) Enable each box to accept the freeze signal to start/stop/re-start all counter registers in that box
e.g., set Cn_MSR_PMON_BOX_CTL.frz_en to 1
Note:
Recommended: set the
.frz_en
bits during the setup phase for each box a user intends
to monitor, and left alone for the duration of the monitoring session.
b) Freeze the box’s counters while setting up the monitoring session.
e.g., set Cn_MSR_PMON_BOX_CTL.frz to 1
For each event to be measured within each box:
c) Enable counting for each monitor
e.g. Set C0_MSR_PMON_CTL2.en to 1
Note:
Recommended: set the .en bit for all counters in each box a user intends to monitor,
and left alone for the duration of the monitoring session.
d) Select event to monitor if the event control register hasn’t been programmed:
