50
Intel
®
Xeon
®
Processor Specification Update
Errata
b. Update the associated cache line state information to shared state on the originating bus
(rather than invalid state) in reaction to a BWIL or BLW.
Status:
For the steppings affected, see the
Summary Table of Changes
.
P81
Control Register 2 (CR2) can be updated during a REP MOVS/STOS instruction with
Fast Strings enabled
Problem:
Under limited circumstances while executing a
REP
MOVS/STOS
string instruction, with fast
strings enabled, it is possible for the value in CR2 to be changed as a result of an interim paging
event, normally invisible to the user. Any higher priority architectural event that arrives and is
handled while the interim paging event is occurring may see the modified value of CR2.
Implication:
The value in CR2 is correct at the time that an architectural page fault is signaled. Intel has not
observed this erratum with any commercially available software.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Table of Changes
.
P82
Writing the Local Vector Table (LVT) when an Interrupt is Pending May
Cause an Unexpected Interrupt
Problem:
If a local interrupt is pending when the LVT entry is written, an interrupt may be taken on the new
interrupt vector even if the mark bit is set.
Implication:
An interrupt may immediately be generated with the new vector when a LVT entry is written, even
if the new LVT entry has the mask bit set. If there is no Interrupt Service Routing (ISR) set up for
that vector the system will GP fault. If the ISR does not do an End of Interrupt (EOI) the bit for the
vector will be left set in the in-service register and mask all interrupts at the same or lower priority.
Workaround:
Any vector programmed into an LVT entry must have an ISR associated with it, even if that vector
was programmed as masked. This ISR routine must do an EOI to clear any unexpected interrupts
that may occur. The ISR associated with the spurious vector does not generate an EOI, therefore
the spurious vector should not be used when writing the LVT.
Status:
For the steppings affected, see the
Summary Table of Changes.
P83
The Processor May Report a #TS Instead of a #GP Fault
Problem:
A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception) instead of a
#GP fault (general protection exception).
Implication:
Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP fault. Intel
has not observed this erratum with any commercially available software.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Table of Changes.
