Intel
®
Xeon
®
Processor Specification Update
41
Errata
1. A read to B misses in the L2 cache and allocates cache line B and its associated second-sector
pre-fetch into an almost full bus queue.
2. A BRL to cache line B completes with HIT# and fills data in Shared (S) state.
3. The bus queue full condition causes the prefetch to cache line A to be canceled, cache line A
will remain M in the WC buffers and I in the L2 while cache line B will be in the S state. Then,
if the further conditions occur:
a. Cache line A is evicted from the WC buffers to the bus queue which is still almost full.
b. A hardware prefetch RFO to cache line B, hits the S state in the L2 and observes cache
line A in the I state, allocates both cache lines.
c. An RFO to cache line A completes before the WC buffers write modified data back,
filling the L2 with stale data.
d. The write-back from the WC Buffers completes leaving stale data, for cache line A, in the
Exclusive (E) state in the L2 cache.
Implication:
Stale data may be consumed leading to unpredictable program execution. Intel has not been able to
reproduce this erratum in commercial software.
Workaround:
It is possible for BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Table of Changes
.
P47
Re-mapping the APIC base address to a value less than or equal to
0xDC001000 may cause I/O and special cycle failure
Problem:
Re-mapping the APIC base address from its default can cause conflicts with either I/O or special
cycle bus transactions.
Implication:
Either I/O or special cycle bus transactions can be redirected to the APIC, instead of appearing on
the front side bus.
Workaround:
Use any APIC base addresses above 0xDC001000 as the relocation address.
Status:
For the steppings affected, see the
Summary Table of Changes
.
P48
Erroneous BIST result found in EAX register after reset
Problem:
The processor may show an erroneous built-in self test (BIST) result in the EAX register bit 0 after
reset.
Implication:
When this erratum occurs, an erroneous BIST failure will be reported in the EAX register bit 0,
however this failure can be ignored since it is not accurate.
Workaround:
It is possible for BIOS to workaround this issue by masking off bit 0 in the EAX register where
BIST results are written.
Status:
For the steppings affected, see the
Summary Table of Changes
.
P49
Processor does not flag #GP on non-zero write to certain MSRs
Problem:
When a non-zero write occurs to the upper 32 bits of IA32_CR_SYSENTER_EIP or
IA32_CR_SYSENTER_ESP, the processor should indicate a general protection fault by flagging
#GP. Due to this erratum, the processor does not flag #GP.
Implication:
The processor unexpectedly does not flag #GP on a non-zero write to the upper 32 bits of
IA32_CR_SYSENTER_EIP or IA32_CR_SYSENTER_ESP. No known commercially available
operating system has been identified to be affected by this erratum.
Workaround:
None at this time.
Status:
For the steppings affected, see the
Summary Table of Changes
.
