Intel
®
Xeon
®
Processor Specification Update
37
Errata
P31
Multiple accesses to the same S-state L2 cache line and ECC error
combination may result in loss of cache coherency
Problem:
When a RFO cycle has a 64 bit address match with an outstanding read hit on a line in the L2 cache
which is in the S-state AND that line contains an ECC error, the processor should recycle the RFO
until the ECC error is handled. Due to this erratum, the processor does not recycle the RFO and
attempt to service both the RFO and the read hit at the same time.
Implication:
When this erratum occurs, cache may become incoherent.
Workaround:
None at this time.
Status:
For the steppings affected, see the
Summary Table of Changes
.
P32
IA32_MC0_ADDR and IA32_MC0_MISC registers will contain invalid or stale
data following a data, address, or response parity error
Problem:
If the processor experiences a data, address, or response parity error, the ADDRV and MISCV bits
of the IA32_MC0_STATUS register are set, but the IA32_MC0_ADDR and IA32_MC0_MISC
registers are not loaded with data regarding the error.
Implication:
When this erratum occurs, the IA32_MC0_ADDR and IA32_MC0_MISC registers will contain
invalid or stale data.
Workaround:
Ignore any information in the IA32_MC0_ADDR and IA32_MC0_MISC registers after a data or
response parity error.
Status:
For the steppings affected, see the
Summary Table of Changes
.
P33
When the processor is in the system management mode (SMM), debug
registers may be fully writeable
Problem:
When in system management mode (SMM), the processor executes code and stores data in the
SMRAM space. When the processor is in this mode and writes are made to DR6 and DR7, the
processor should block writes to the reserved bit locations. Due to this erratum, the processor may
not block these writes. This may result in invalid data in the reserved bit locations.
Implication:
Reserved bit locations within DR6 and DR7 may become invalid.
Workaround:
Software may perform a read/modify/write when writing to DR6 and DR7 to ensure that the value
in the reserved bits is maintained.
Status:
For the steppings affected, see the
Summary Table of Changes
.
P34
Associated counting logic must be configured when using event selection
control (ESCR) MSR
Problem:
ESCR MSRs allow software to select specific events to be counted, with each ESCR usually
associated with a pair of performance counters. ESCRs may also be used to qualify the detection of
at-retirement events that support precise-event-based sampling (PEBS). A number of performance
metrics that support PEBS require a 2nd ESCR to tag uops for the qualification of at-retirement
events. (The first ESCR is required to program the at-retirement event.) Counting is enabled via
counter configuration control registers (CCCR) while the event count is read from one of the
associated counters. When counting logic is configured for the subset of at-retirement events that
require a 2nd ESCR to tag uops, at least one of the CCCRs in the same group of the 2nd ESCR
must be enabled.
Implication:
If no CCCR/counter is enabled in a given group, the ESCR in that group that is programmed for
tagging uops will have no effect. Hence a subset of performance metrics that require a 2nd ESCR
for tagging uops may result in 0 count.
Workaround:
Ensure that at least one CCCR/counter in the same group as the tagging ESCR is enabled for those
performance metrics that require 2 ESCRs and tagging uops for at-retirement counting.
