42
Intel
®
Xeon
®
Processor Specification Update
Errata
P50
Simultaneous assertion of A20M# and INIT# may result in incorrect data
fetch
Problem:
If A20M# and INIT# are simultaneously asserted by software, followed by a data access to the
0xFFFFFXXX memory region, with A20M# still asserted, incorrect data will be accessed. With
A20M# asserted, an access to 0xFFFFFXXX should result in a load from physical address
0xFFEFFXXX. However, in the case of A20M# and INIT# being asserted together, the data load
will actually be from the physical address 0xFFFFFXXX. Code accesses are not affected by this
erratum.
Implication:
Processor may fetch incorrect data, resulting in BIOS failure.
Workaround:
Deasserting and reasserting A20M# prior to the data access will workaround this erratum.
Status:
For the steppings affected, see the
Summary Table of Changes
.
P51
Processor does not respond to break requests from ITP
Problem:
On power-up and low-power state transitions, the processor's TAP circuitry may remain in the tap-
logic-reset (TLR) state.
Implication:
The ITP is unable to cause a break on reset in the processor, which may prevent the loading of
processor and chipset registers, or affect the ability to debug from cold boot and low power
transitions
Workaround:
None at this time.
Status:
For the steppings affected, see the
Summary Table of Changes
.
P52
Glitches on address and data strobe signals may cause system shutdown
Problem:
When the Processor Signature instruction is executed with EAX = 2 on a processor without HT
Technology or with HT Technology disabled via power on configuration, it should return a value
of 51h in EAX[15:8] to indicate that the instruction translation lookaside buffer (ITLB) has 128
entries. On a processor with HT Technology enabled, the processor should return 50h (64 entries).
Due to this erratum, the Processor Signature instruction always returns 50h (64 entries).
Implication:
Software may incorrectly report the number of ITLB entries. Operation of the processor is not
affected.
Workaround:
None at this time.
Status:
For the steppings affected, see the
Summary Table of Changes
.
P53
A write to an APIC Register Sometimes May Appear to Have Not Occured
Problem:
With respect to the retirement of instructions, stores to the uncacheable memory-based APIC
register space are handled in a non-synchronized way. For example if an instruction that masks the
interrupt flag, e.g. CLI, is executed soon after an uncacheable write to the Task Priority Register
(TPR) that lowers the APIC priority, the interrupt masking operation may take effect before the
actual priority has been lowered. This may cause interrupts whose priority is lower than the initial
TPR, but higher than the final TPR, to not be serviced until the interrupt enabled flag is finally set,
i.e. by STI instruction. Interrupts will remain pending and are not lost.
Implication:
In this example the processor may allow interrupts to be accepted but may delay their service.
Workaround:
This non-synchronization can be avoided by issuing an APIC register read after the APIC register
write. This will force the store to the APIC register before any subsequent instructions are
executed. No commercial operating system is known to be impacted by this erratum.
Status:
For the steppings affected, see the
Summary Table of Changes.
