Intel SE7500CW2, Технические характеристики продукции

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Error Reporting and Handling SE7500CW2 Server Board Technical Product Specification
76
Revision 1.40
97h Boot to Full DOS
7.1.2 BIOS POST Beep Codes
The following tables lists POST error beep codes. Prior to system video initialization, the BIOS
uses these beep codes to inform users of error conditions.
The beep code occurs only when a critical error or BIOS fails to boot to the operating system.
Please note that not all error conditions are supported by BIOS Beep codes.
The following list contains some of the beep codes used in SE7500CW2 platform:
•
Memory error: A unique beep-code is derived from the port 80h code as follows:
-
The 8-bit error code is broken down to four 2-bit groups.
-
Each group is made one-based (through 4)
- Short beeps are generated for the number of times in each group.
Example:
Port 80h = 0E1h is divided into:
11 10 00 01 or 4-3-1-2 beep code
•
Two short beeps: CMOS checksum bad been found and load default.
•
Five short beeps: Clear CMOS SW is on.
•
One short beep: BIOS will boot to the operating system.
Table 37: POST Error Beep Codes
Beeps Reason
4-3-1-2 No memory DIMM(s)
4-3-1-3 Memory type is mismatch
4-3-1-4 No DIMM Pair(s) in System
4-3-3-1 Memory Error Row Address Bits
4-3-3-2 Memory Error Internal Banks
4-3-3-3 Memory Error Timing
4-3-3-4 Memory Error Register CAS 3
4-3-4-1 Memory Error Register NonReg Mix
4-3-4-2 Memory Error CAS Latency
4-3-4-3 Memory Error Size Not Supported