Intel Pentium III, Руководство по конструкции

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Intel
®
Pentium
®
III Processor with 512KB L2 Cache Dual Processor Platform Design Guide 3-1
Processor Host Bus Design
3
3.1 Initial Timing Analysis
To determine the available flight time window, perform an initial timing analysis. Analysis of setup and
hold conditions will determine the minimum and maximum flight time bounds for the system bus. Use the
following equations to establish the system flight time limits.
Component timings for the Intel
®
Pentium
®
III Processor with 512KB L2 Cache are available in the Intel
®
Pentium
®
III Processor with 512KB L2 Cache Datasheet. Please contact your chipset vendor for
documentation concerning the chipset component timing.
Table 3-1. System Timing Equations
Equation
T
flight,min
>= T
hold
- T
co,min
+ T
skew
T
flight,max
<= T
cycle
- T
co,max
- T
su
- T
skew
- T
jit
- T
adj
Table 3-2. System Timing Terms
Term Description
T
cycle
System cycle time, defined as the reciprocal of the frequency.
T
flight,min
Minimum system flight time.
T
flight,max
Maximum system flight time.
T
co,max
Maximum driver delay from input clock to output data.
T
co,min
Minimum driver delay from input clock to output data.
T
su
Minimum setup time. Defined as the time for which the input data must be valid prior to the
input clock.
T
hold
Minimum hold time. Defined as the time for which the input data must remain valid after the
input clock.
T
skew
Clock generator skew. Defined as the maximum delay variation between output clock
signals from the system clock generator, the maximum delay variation between clock
signals due to system board variation and chipset loading variation, and skew due to delay
in the PGA370 socket.
T
jit
Clock jitter. Defined as the maximum edge to edge variation in a given clock signal.
T
adj
Multi-bit timing adjustment factor. This term accounts for the additional delay that occurs in
the network when multiple data bits switch in the same cycle. The adjustment factor
includes such mechanisms as package and PCB crosstalk, high inductance current return
paths, and simultaneous switching noise.