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8-4

Intel

®

Pentium

®

III Processor with 512KB L2 Cache Dual Processor Platform Design Guide

8.6

Miscellaneous Checklist for 370-Pin Socket
Processors

Host bus clocks are critical. Signal integrity and timing of these signals should be carefully evaluated and
simulated. It is strongly recommended that system bus clocks be routed on signal layers next to the
ground layer and do not traverse multiple signal layers. Please see Chapter 4 for details.

Table 8-4. Clock Signals

CPU Pin

Pin Connection

BCLK

BCLK#/CLKREF

For single ended clocking connect BCLK to clock generator through 22 - 33

Ω

series resistor (OEM must simulate based on driver characteristics). Connect
BCLK# to a filtered 1.25 V supply.To reduce pin-to-pin skew, tie host clock
outputs together at the clock driver then route to both processors and chipset.

For differential clocking signals must be length matched from the receivers to a
resistive network, and from the network to the receiver. The resistive network
consists of a 33.2

Ω 1%

series resistor on each line, and a 475

Ω

resistor

between them. Lastly both lines are pulled down with a 63.4

Ω 1%

resistor to

GND. See Chapter 4 for more details.

PICCLK

Must be connected from the clock generator to the PICCLK pin on the CPUs.
Voltage divider circuitry should yield 2.0 V (OEM must simulate based on driver
characteristics).

Table 8-5. Miscellaneous Signals

CPU Pin

Pin Connection

BSEL0

For single ended clocking connect to clock generator ONLY. Pull up to 3.3 V with
a 1 K

Ω

resistor. NC on processor 0 and 1.

For differential clocking connect BSEL0 on CPU0 to BSEL0 on CPU1, pull up to
3.3 V with a 1 K

Ω

resistor, connect to clock generator

BSEL1

For single ended clocking connect to clock generator ONLY. Pull up to 3.3 V with
a 1 K

Ω

resistor. NC on processor 0 and 1.

For differential clocking connect BSEL1 on CPU0 to BSEL1 on CPU1, pull up to
3.3 V with a 1 K

Ω

resistor, connect to clock generator.

CPUPRES#

Tie to GND, leave it N/C, or could be connected to powergood logic to gate
system from powering on if no processor is present.

DETECT

Leave unconnected or connect to Vss

KEY

Connect to Vss.

NCHCTRL

Pull up through 14

Ω

to V

TT

.

THERMDN

Thermal diode cathode. Connect to thermal sensor device.

THERMDP

Thermal diode anode. Connect to thermal sensor device.

RTTCTRL

68

Ω

1% pull-down to GND.

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Содержание Pentium III

Страница 1: ...Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide June 2001 Document Number 249658 001...

Страница 2: ...e definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them This document contains information on products in the design phase of de...

Страница 3: ...eakout 3 7 3 7 4 Minimizing Crosstalk 3 8 3 8 Layout Rules for Non AGTL CMOS Signals 3 8 3 9 Undershoot Overshoot Requirements 3 9 3 10 Debug Port Routing Guidelines 3 9 3 10 1 Target System Implement...

Страница 4: ...7 3 7 4 Pinout Changes 7 4 7 5 Dual Processor Specific Pin Recommendations 7 6 7 5 1 DETECT AF36 7 6 7 5 2 RESET2 AJ3 7 6 7 5 3 KEY AM2 7 6 7 6 AGTL Bus Transition 7 6 7 7 Host Bus Layout Changes 7 7...

Страница 5: ...Clocking Topology Chipset 4 3 4 4 CLKREF Filter Implementation 4 4 4 5 Single Ended Clock BSEL Circuit 4 5 4 6 Differential Clocking Topology 4 6 4 7 Differential Clock BSEL Circuit 4 7 4 8 Debug Port...

Страница 6: ...out Guidelines 3 10 3 11 JTAG Signal Layout Guidelines 3 11 3 12 Execution Signals Routing Guidelines 3 11 3 13 Debug Port Termination Requirement 3 13 3 14 Routing Guidelines 3 13 4 1 Component Value...

Страница 7: ...Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide vii Revision History Revision Draft Changes Date 001 Initial Version June 2001...

Страница 8: ...This page intentionally left blank...

Страница 9: ...ebug recommendations and system checklist presented in this document These design guidelines have been developed to ensure maximum flexibility for board designers while reducing the risk of board rela...

Страница 10: ...B L2 Cache and some Intel Pentium III Processors CPUID 068xh for the PGA370 socket The FC PGA2 package contains an Integrated Heat Spreader which covers the processor die Keep out zone The area on or...

Страница 11: ...III Processor with 512KB L2 Cache Dual Processor Platform Design Guide 1 3 1 4 State of the Data The data contained within this document are based on near production validation testing and silicon cha...

Страница 12: ...This page intentionally left blank...

Страница 13: ...es When calculating flight times it is important to consider the minimum and maximum impedance of a trace based on the switching of neighboring traces Using wider spaces between the traces can minimiz...

Страница 14: ...lane should not be split on the ground plane layer Keep vias for decoupling capacitors as close to the capacitor pads as possible 2 2 Socket 370 Component Keepout Figure 2 2 Socket 370 Component Keepo...

Страница 15: ...Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide 2 3 Figure 2 3 Socket 370 Volumetric Keepout...

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Страница 17: ...cy Tflight min Minimum system flight time Tflight max Maximum system flight time Tco max Maximum driver delay from input clock to output data Tco min Minimum driver delay from input clock to output da...

Страница 18: ...ed against the latest specifications before proceeding with analysis 3 2 General Topology and Layout Guidelines Intel is recommending that all Intel Pentium III Processor with 512KB L2 Cache dual proc...

Страница 19: ...Table 3 6 contains the component values which should be used for this topology Figure 3 1 System Bus T Topology Table 3 5 Trace Lengths for T Topology ServerWorks Chipset Segment Min Length inches Ma...

Страница 20: ...pin The R4 value for CPU1 uses a 100 resistor pulled down to Vss instead of the 68 that is normally recommended CPU0 s R3 value should remain 68 Please Note Intel will not be validating the terminato...

Страница 21: ...xamine the signal integrity of these signals and optionally implement the circuit shown in Figure 3 3 This recommendation will work correctly for systems designed with the standard T topology or the t...

Страница 22: ...ut has a larger impact on the signal flight times Intel recommends a value of 150 10 as a reasonable trade off between dampening and flight time Figure 3 3 Wired OR Termination Topology Table 3 9 Wire...

Страница 23: ...mils The L0 and L1 lengths in Table 3 5 should be matched to within 0 25 inches Minimize the number of vias and layer transitions 3 7 Layout Rules for AGTL Signals 3 7 1 Ground Reference It is strongl...

Страница 24: ...nce plane which minimizes the crosstalk Route AGTL address data and control signals in separate groups to minimize crosstalk between groups Keep at least 25 mils between each group of signals Minimize...

Страница 25: ...ay yield excessive overshoot undershoot Refer to the latest Intel Pentium III Processor with 512KB L2 Cache Datasheet for detailed undershoot overshoot requirements 3 10 Debug Port Routing Guidelines...

Страница 26: ...nt of DC shifting on these signals This is due to the small termination values that are recommended for these signals 3 10 1 1 1 System Signal Layout Guidelines Table 3 10 provides the system signal l...

Страница 27: ...l Routing Notes Sample Layout TCK Critical JTAG signals which requires timing and signal integrity considerations driver is 74VCX16245 with external edge rate control on TCK Figure 3 5 TMS TDI TDO Cri...

Страница 28: ...3 12 Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide Figure 3 6 PRDYx Signal Termination Figure 3 7 RESET Signal Termination...

Страница 29: ...and routing requirements BSEN 240 N A VCC DBRESET 240 N A VCC DBINST 10 K N A VCC JTAG Signals TCK 39 GND TDI 200 300 N A VCCCMOS1 5 TDO 150 N A VCCCMOS1 5 TMS 39 N A VCCCMOS1 5 TRST 500 680 N A GND...

Страница 30: ...igure 3 9 and Figure 3 10 illustrate possible bypass configurations with a three pin jumper and a four pin jumper TRST Figure 3 4b 1 max from debug port to RT AND 12 max from debug port to processor P...

Страница 31: ...Intel Pentium III Processor with 512KB L2 Cache Dual Processor Platform Design Guide 3 15 Figure 3 9 TDO 3 Pin Jumper Bypass Figure 3 10 4 Pin Jumper Bypass...

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Страница 33: ...ould be followed for the host bus clocks It is recommended that system bus clocks be routed on the signal layer next to the ground layer referenced to ground It is strongly recommended that system bus...

Страница 34: ...with 512KB L2 Cache dual processor platforms have support for using single ended host bus clock drivers When using this clocking method the BCLK signal pin W37 is used as the single ended clock input...

Страница 35: ...ng Topology CPU Table 4 1 Component Values for SE Clocking Topology CPU Reference Value Notes L0 0 25 to 0 5 inches All L0s should be matched L1 Chipset L1 1 0 125 Chipset L1 0 5 0 125 Use this proces...

Страница 36: ...inches 4 2 1 CLKREF Filter Implementation When using single ended clocking mode the BCLK CLKREF signal on the processor serves as a reference voltage to the clock input To provide a steady reference...

Страница 37: ...r into 133 MHz clocking mode and will only support 133 MHz capable processors 4 3 Differential Host Bus Clocking Routing Intel Pentium III Processor with 512KB L2 Cache dual processor platforms suppor...

Страница 38: ...Place all termination resistors within 0 40 inches of BCLK BCLK pins at the receiver Other should be spaced at least 20 mils away from clock lines All the termination resistors are rated as 1 accuracy...

Страница 39: ...0 and RESET signals from the nearest front side bus agent System designers should record the flight time of the BPM 5 0 and RESET signals from the nearest front side bus agent to the Debug Port This v...

Страница 40: ...longer than the processor clock trace s L0 lengths The terminating resistors should be placed as close the ITP socket as possible 4 5 Clock Driver Decoupling and Power Delivery The decoupling and powe...

Страница 41: ...essor with 512KB L2 Cache core and cache supply voltages VTT refers to the AGTL termination voltage AGTL refers to Intel Pentium III Processor with 512KB L2 Cache s Assisted Gunning Transceiver Logic...

Страница 42: ...e guidelines in VRM 8 5 DC DC converter design guidelines document Each regulator circuit should be placed as close as possible to the corresponding processor and aligned to the side of the socket wit...

Страница 43: ...the Intel Pentium III Processor with 512KB L2 Cache Datasheet for voltage tolerance specifications Failure to meet these specifications on the low end tolerance results in transistors slowing down an...

Страница 44: ...L2 Cache Datasheet for the voltage sequencing requirements 5 4 Meeting Power Requirements Intel recommends using VRM 8 5 compliant modules or embedded regulator designs for Intel Pentium III Processo...

Страница 45: ...re correctly the bulk capacitors in the system slow the transient requirement seen by the power source to a rate that it is able to supply while the high frequency capacitors slow the transient requir...

Страница 46: ...on VRMs are effectively electrically located behind the inductance of the converter pins As a result bulk capacitors need to be utilized close to the processor socket The recommended number of bulk de...

Страница 47: ...2 VTT Decoupling Design Twenty 0 1 F capacitors in 0603 packages should be placed within 200 mils of each PGA370 socket As many of these capacitors should be placed inside the PGA370 socket cavity 5...

Страница 48: ...ted through a capacitor 22 to 100 F to PLL1 See Figure 5 7 Other routing requirements The capacitor C should be close to the PLL1 and PLL2 pins 0 1 per route The PLL2 route should be parallel and next...

Страница 49: ...ure 5 8 Other requirements Use shielded type inductor to minimize magnetic pickup Filter should support DC current 30mA DC voltage drop from VCC to PLL1 should be 60mV which in practice implies series...

Страница 50: ...This page intentionally left blank...

Страница 51: ...2 THERMTRIP Erratum Intel has identified an issue with THERMTRIP which may incorrectly assert during de assertion of RESET at nominal operating temperatures in Intel Pentium III Processors with 512KB...

Страница 52: ...ions must be found if such test capability is required NOTES 1 For Production Boards Depopulate R5 2 To use ITP Install R5 Depopulate R4 3 Assumes the inputs to the CPU_PWRGD are open collector signal...

Страница 53: ...III Processor with 512KB L2 Cache operation the designer must ensure that the requirements in this guideline are fully satisfied 7 2 Implement VRM 8 5 The Intel Pentium III Processor with 512KB L2 Cac...

Страница 54: ...VRM guidelines outlined in the VRM 8 5 DC DC Converter Design Guidelines In particular the voltage regulator must be able to respond to the transient and static loads specified in Figure 7 2 Figure 7...

Страница 55: ...e FC PGA2 The FC PGA2 package leverages the previous FC PGA package technology used on previous PGA370 socket processors The FC PGA2 package adds an Integrated Heat Spreader IHS to improve heat conduc...

Страница 56: ...B L2 Cache have changed from their AGTL only processor definitions A summary of these changes are provided in Table 7 1 The platform must implement the pinout changes shown below to be compatible with...

Страница 57: ...platforms and is keyed accordingly Figure 7 4 shows how this feature works for an Intel Pentium III Processor with 512KB L2 Cache in an AGTL only processor platform and in an Intel Pentium III Process...

Страница 58: ...d in reset by this pin Intel recommends the KEY pin be connected to ground in Intel Pentium III Processor with 512KB L2 Cache dual processor platforms to allow this electronic key feature to work corr...

Страница 59: ...ntel Pentium III Processor CPUID 068xh with AGTL Capability are available from the Intel Developer Website Please contact chipset vendors for buffer models for their products 7 8 Single Ended Clocking...

Страница 60: ...l Pentium III Processor with 512KB L2 Cache the VID and BSEL signals are true open drain CMOS outputs and are no longer shorts or opens to VSS Because of this these signals now need to be pulled up to...

Страница 61: ...a legacy or single ended clock driver system A complex circuit to delay power delivery to the clock drivers and chipsets is needed to allow for dynamic BSEL operation Intel will not be pursuing such a...

Страница 62: ...This page intentionally left blank...

Страница 63: ...s next to the ground layer It is important to provide effective signal return paths with low inductance Table 8 1 AGTL Signals Sheet 1 of 2 CPU Pin Pin Connection A 35 3 Connect to chipset and second...

Страница 64: ...chipset and second CPU TRDY Connect to chipset and second CPU Table 8 2 CMOS Signals Sheet 1 of 2 CPU Pin Pin Connection A20M Connect to second CPU and pull up through 330 to VccCMOS May also need to...

Страница 65: ...he PWRGOOD logic SLP Connect to second CPU and pull up through 330 to VccCMOS1 5 May also need to be connected to chipset or compatibility logic SMI Connect to second CPU and pull up through 330 to Vc...

Страница 66: ...or between them Lastly both lines are pulled down with a 63 4 1 resistor to GND See Chapter 4 for more details PICCLK Must be connected from the clock generator to the PICCLK pin on the CPUs Voltage d...

Страница 67: ...nected to 2 5 V voltage source Should have some high and low frequency decoupling VccCMOS1 8 Connected to 1 8V voltage source Should have some high and low frequency decoupling VCCCORE Connect to core...

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