Intel Pentium III, Руководство по конструкции

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Intel
®
Pentium
®
III Processor with 512KB L2 Cache Dual Processor Platform Design Guide 7-7
The termination resistors for the Intel
®
Pentium
®
III Processor with 512KB L2 Cache AGTL signaling are
integrated into the processor package. This is similar to AGTL+ only processor implementation. The Rtt
reference resistor is to be set to 56 ohms in a uni-processor platform and 68 ohms in a dual processor
platform. This is different than the previous AGTL+ only processor platforms that have a range of
allowable Rtt values.
For dual processor platforms with only one processor populated, a terminator must be plugged into the
empty socket to maintain the correct termination of the host bus. The specifications for this terminator are
contained the Intel
®
Pentium
®
III Processor with 512KB L2 Cache Bus Terminator Design Guide. The
AGTL+ only processor platform terminator will not work in an Intel
®
Pentium
®
III Processor with 512KB
L2 Cache platform because of the pin differences. Please consult the Intel Developer Website for vendor
information.
7.7 Host Bus Layout Changes
The host bust routing recommendations may be different in an Intel
®
Pentium
®
III Processor with 512KB
L2 Cache dual processor system than previous socket 370 dual processor designs. Intel recommends
using the routing guidelines presented in this document for Intel
®
Pentium
®
III Processor with 512KB L2
Cache dual processor systems. Intel also recommends careful simulation of the host bus to verify a
design’s timing parameters.
The IBIS models for the Intel
®
Pentium
®
III Processor with 512KB L2 Cache and Intel
®
Pentium
®
III
Processor (CPUID 068xh) with AGTL Capability are available from the Intel Developer Website. Please
contact chipset vendors for buffer models for their products.
7.8 Single Ended Clocking Support
The Intel
®
Pentium
®
III Processor with 512KB L2 Cache supports both 1.0V differential and 2.5V single-
ended (SE) clocking. The processor will auto-detect the clocking method in use by monitoring the Y33
(BLCK#) pin for activity at reset. The clocking specifications for differential and SE clocking can be found
in the Intel
®
Pentium
®
III Processor with 512KB L2 Cache Datasheet. The specifications for SE clocking
in the Intel
®
Pentium
®
III Processor with 512KB L2 Cache platform are more constrained than the
previous AGTL+ only processor platform. This tighter timing specification is to allow SE clocking to
maintain frequency parity with differential clocking. The processor clocking circuitry of any legacy
platform that is being updated for Intel
®
Pentium
®
III Processor with 512KB L2 Cache support should be
closely examined to ensure it meets the tighter timing specification.
Intel expects only minor modifications to existing high quality clock drivers to meet the new timing
specification. Please contact your chipset vendor for clock vendor information.
7.9 VID & BSEL Signals
The Intel
®
Pentium
®
III Processor with 512KB L2 Cache introduces a new implementation of the VID and
BSEL signals. The VID and BSEL signals are now volatile and are only valid after the qualifying signal,
DYN_OE is active. The logic that sets these signals to the correct value is powered by VTT, so they will
be unstable when power is first applied. Therefore, the VID and BSEL signals should only be sampled
after DYN_OE is active, indicating that these outputs are now in a valid state.