Intel Pentium III, Руководство по конструкции

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Intel
®
Pentium
®
III Processor with 512KB L2 Cache Dual Processor Platform Design Guide 5-5
5.4.2 Decoupling Technology and Transient Response
The inductance of the system due to cables and power planes slows the power supply's ability to
respond quickly to a current transient. Decoupling a power plane can be broken into several independent
parts. The closer to the load the capacitor is placed, the more inductance that is bypassed. By bypassing
the inductance of leads, power planes, etc., less capacitance is required. However, closer to the load
there is less room for capacitance. Therefore trade-offs must be made.
The Intel
®
Pentium
®
III Processor with 512KB L2 Cache causes large switching transients. These sharp
surges of current occur at the transition between low power mode and high power mode. It is the
responsibility of the system designer to provide adequate high frequency decoupling to manage the
highest frequency components of the current transients. To lower total board inductance and resistance,
the processor is designed with approximately 74 Vcc
CORE
and 74 V
SS
(ground) pins. Larger bulk storage
(C
BULK
), such as electrolytic (OSCON) capacitors, supply current during longer lasting changes in
current demand by the component, such as coming out of an idle condition. Similarly, they act as a
storage well for current when entering an idle condition from a running condition.
Power bypassing is required due to the relatively slow speed at which a DC-to-DC converter can react,
that is the loop response time of the converter feedback circuit in comparison to the processor load
change and frequency. Bulk capacitance supplies energy from the time the high frequency decoupling
capacitors are drained until the power supply can react to the demand. More correctly, the bulk
capacitors in the system slow the transient requirement seen by the power source to a rate that it is able
to supply, while the high frequency capacitors slow the transient requirement seen by the bulk capacitors
to a rate that they can supply.
A load-change transient occurs when coming out of or entering a low power mode. These are not only
quick changes in current demand, but also long lasting average current requirements. Maintaining
voltage tolerance during these changes in current requires high-density bulk capacitors with low Effective
Series Resistance (ESR) and low Effective Series Inductance (ESL). Use thorough analysis when
choosing these components.
5.4.2.1 Location of High Frequency Decoupling
A system designer for Intel
®
Pentium
®
III Processors with 512KB L2 Cache should properly design for
high frequency decoupling. High frequency decoupling should be placed as close to the power pins of
the processor as physically possible. Use both sides of the board if necessary for placing components in
order to achieve the optimum proximity to the power pins. This is vital as the inductance of the board's
metal plane layers could cancel the usefulness of these low inductance components.
Another method to lower the inductance that should be considered is to shorten the path from the
capacitor pads to the pins that it is decoupling. If possible, place the vias connecting to the planes within
the pad of the capacitor. If this is not possible, keep the traces as short and wide as is feasible. Possibly
one or both ends of the capacitor can be connected directly to the pin of the processor without the use of
via. Even if simulation results look good, these practical suggestions can be used to create an even
better decoupling situation where they can be applied in layout.
Figure 5-5 illustrates these concepts..
Figure 5-5. 1206 Capacitor Pad and Via Layouts
Bad
Vias
Very Good
Very Good
Pads
Capacitors
Good
Pin
Less Bad