PD672X/30/32/33 — ZV Port Implementation
14
Application Note
23
A6
I
MCLK
I
103
178
Audio MCLK PCM signal
24–25
A[5:4]
I
RESERVED
RFU
105, 107
181, 183
Tristated by Controller; no
connection in PC Card
26–29
A[3:0]
I
ADDRESS
[3:0]
I
109,111,
113,116
185,187,
189, 191
Used for accessing PC Card
33
IOIS16#
O
PCLK
O
125
201
Pixel clock to ZV Port
46
A17
I
Y1
O
83
158
Video data to ZV Port
47
A18
I
Y3
O
85
161
Video data to ZV Port
48
A19
I
Y5
O
88
164
Video data to ZV Port
49
A20
I
Y7
O
90
166
Video data to ZV Port
50
A21
I
UV0
O
92
168
Video data to ZV Port
53
A22
I
UV1
O
94
170
Video data to ZV Port
54
A23
I
UV3
O
96
172
Video data to ZV Port
55
A24
I
UV5
O
99
174
Video data to ZV Port
56
A25
I
UV7
O
102
176
Video data to ZV Port
60
INPACK#
O
LRCLK
O
110
186
Audio LRCLK PCM signal
62
SPKR#
O
SDATA
O
114
190
Audio PCM Data signal
Table 3. PC Card, ZV Port, and PD6730/’6832 Pin Assignment (Sheet 2 of 2)
PC Card
Pin No.
PC Card
Pin
I/O in PC
Card
Mode
ZV Port Pin
Name
I/O in ZV
Port Mode
PD6730 or
PD6832
Socket A
PD6730 or
PD6832
Socket B
Comments
NOTE: ‘I’ indicates that the signal is an input to the PC Card; ‘O’ indicates that the signal is an output from the PC Card.
Controller ignores BVD2/SPKR#, IOIS16#, and INPACK# during ZV Port operation.
