Figure 2.
Nios II Processor Core Block Diagram
Exception
Controller
Internal
Interrupt
Controller
Arithmetic
Logic Unit
General
Purpose
Registers
Control
Registers
Nios II Processor Core
reset
clock
JTAG
interface
to software
debugger
Custom
I/O
Signals
irq[31..0]
JTAG
Debug Module
Program
Controller
&
Address
Generation
Custom
Instruction
Logic
Data Bus
Tightly Coupled
Data Memory
Tightly Coupled
Data Memory
Data
Cache
Instruction
Cache
Instruction Bus
Tightly Coupled
Instruction Memory
Tightly Coupled
Instruction Memory
cpu_resetrequest
cpu_resettaken
Memory
Management
Unit
Translation
Lookaside
Buffer
Instruction
Regions
Memory
Protection
Unit
Data
Regions
External
Interrupt
Controller
Interface
eic_port_data[44..0]
eic_port_valid
Shadow
Register
Sets
Required
Module
Optional
Module
Key
2.1. Processor Implementation
The functional units of the Nios II architecture form the foundation for the Nios II
instruction set. However, this does not indicate that any unit is implemented in
hardware. The Nios II architecture describes an instruction set, not a particular
hardware implementation. A functional unit can be implemented in hardware,
emulated in software, or omitted entirely.
A Nios II implementation is a set of design choices embodied by a particular Nios II
processor core. All implementations support the instruction set defined in the
Instruction Set Reference chapter.
Each implementation achieves specific objectives, such as smaller core size or higher
performance. This flexibility allows the Nios II architecture to adapt to different target
applications.
2. Processor Architecture
NII-PRG | 2018.04.18
Nios II Processor Reference Guide
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