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Signal Definitions

IERR#

IERR# (Internal Error) is asserted by a processor as the result of an

internal error. Assertion of IERR# is usually accompanied by a

SHUTDOWN transaction on the processor FSB. This transaction may

optionally be converted to an external error signal (e.g., NMI) by

system core logic. The processor will keep IERR# asserted until the

assertion of RESET#.
This signal does not have on-die termination.

IGNNE#

IGNNE# (Ignore Numeric Error) is asserted to force the processor to

ignore a numeric error and continue to execute noncontrol floating-

point instructions. If IGNNE# is deasserted, the processor generates

an exception on a noncontrol floating-point instruction if a previous

floating-point instruction caused an error. IGNNE# has no effect when

the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of

this signal following an I/O write instruction, it must be valid along

with the TRDY# assertion of the corresponding I/O write bus

transaction.

INIT#

INIT# (Initialization), when asserted, resets integer registers inside

all processors without affecting their internal caches or floating-point

registers. Each processor then begins execution at the power-on

Reset vector configured during power-on configuration. The processor

continues to handle snoop requests during INIT# assertion. INIT# is

an asynchronous signal and must connect the appropriate pins of all

processor FSB agents.

LINT[1:0]

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins

of all FSB agents. When the APIC functionality is disabled, the

LINT0/INTR signal becomes INTR, a maskable interrupt request

signal, and LINT1/NMI becomes NMI, a nonmaskable interrupt. INTR

and NMI are backward compatible with the signals of those names on

the Pentium

processor. Both signals are asynchronous.

These signals must be software configured via BIOS programming of

the APIC register space to be used either as NMI/INTR or LINT[1:0].

Because the APIC is enabled by default after Reset, operation of

these pins as LINT[1:0] is the default configuration.

LL_ID[1:0]

The LL_ID[1:0] signals are used to select the correct loadline slope

for the processor. These signals are not connected to the processor

die.

LOCK#

I/O

LOCK# indicates to the system that a transaction must occur

atomically. This signal must connect the appropriate pins of all

processor FSB agents. For a locked sequence of transactions, LOCK#

is asserted from the beginning of the first transaction to the end of

the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of

the processor FSB, it will wait until it observes LOCK# deasserted.

This enables symmetric agents to retain ownership of the processor

FSB throughout the bus locked operation and ensure the atomicity of

lock.

MCERR#

I/O

MCERR# (Machine Check Error) is asserted to indicate an

unrecoverable error without a bus protocol violation. It may be driven

by all processor FSB agents.
MCERR# assertion conditions are configurable at a system level.

Assertion options are defined by the following options:

• Enabled or disabled.
• Asserted, if configured, for internal errors along with IERR#.
• Asserted, if configured, by the request initiator of a bus

transaction after it observes an error.

• Asserted by any bus agent when it observes an error in a bus

transaction.

For more details regarding machine check architecture, refer to the

Intel

64 and IA-32 Architectures Software Developer’s Manual,

Volume 3.

Table 5-1.

Signal Definitions (Sheet 5 of 8)

Name

Type

Description

Notes

Содержание L5310 - Cpu Xeon Quad-Core Lv 1.6Ghz Fsb1066Mhz 8M Fc-Lga6 Tray

Страница 1: ...318590 005 Dual Core Intel Xeon Processor 5200 Series Datasheet August 2008...

Страница 2: ...h may cause the product to deviate from published specifications Current characterized errata are available on request 64 bit computing on Intel architecture requires a computer system with a processo...

Страница 3: ...1 DC Characteristics 24 2 10 2 Input Device Hysteresis 25 2 11 Mixing Processors 26 2 12 Absolute Maximum and Minimum Ratings 26 2 13 Processor DC Specifications 27 2 13 1 Flexible Motherboard Guidel...

Страница 4: ...op Grant Snoop State 96 7 3 Enhanced Intel SpeedStep Technology 97 8 Boxed Processor Specifications 99 8 1 Introduction 99 8 2 Mechanical Specifications 101 8 2 1 Boxed Processor Heat Sink Dimensions...

Страница 5: ...Coordinates Top View 45 3 7 Processor Land Coordinates Bottom View 46 6 1 Dual Core Intel Xeon Processor E5200 Series Thermal Profile 77 6 2 Dual Core Intel Xeon Processor X5200 Series Thermal Profile...

Страница 6: ...e Loading Specifications 43 3 2 Package Handling Guidelines 44 3 3 Processor Materials 44 4 1 Land Listing by Land Name 47 4 2 Land Listing by Land Number 57 5 1 Signal Definitions 67 6 1 Dual Core In...

Страница 7: ...Added product information for Dual Core Intel Xeon Processor L5238 March 2008 003 Added product information for Dual Core Intel Xeon Processor L5200 Series April 2008 004 Corrected L1 cache size Expo...

Страница 8: ...8 Dual Core Intel Xeon Processor 5200 Series Datasheet...

Страница 9: ...include Intel Wide Dynamic Execution enhanced floating point and multi media units Streaming SIMD Extensions 2 SSE2 Streaming SIMD Extensions 3 SSE3 and Streaming SIMD Extensions 4 1 SSE4 1 Advanced D...

Страница 10: ...latform design guidelines for implementation details The Dual Core Intel Xeon Processor 5200 Series supports either 1333 MHz or 1600 MHz Front Side Bus operations The FSB utilizes a split transaction...

Страница 11: ...used to call out specifications that are unique to the Dual Core Intel Xeon Processor E5200 Series SKU Dual Core Intel Xeon Processor L5200 Series Intel 64 bit microprocessor intended for dual proces...

Страница 12: ...ose Processors may be sealed in packaging or exposed to free air Under these conditions processor lands should not be connected to any supply voltages have any I Os biased or receive any clocks Upon e...

Страница 13: ...tact your Intel representative for the latest revision of these documents 2 Document is available publicly at http developer intel com Document Document Number1 Notes AP 485 Intel Processor Identifica...

Страница 14: ...14...

Страница 15: ...4X front side bus signaling group and GTLREF_ADD is used for the 2X and common clock front side bus signaling groups Both GTLREF_DATA and GTLREF_ADD must be generated on the baseboard See Table 2 18...

Страница 16: ...istance ESR and the baseboard designer must assure a low interconnect resistance from the regulator EVRD or VRM pins to the LGA771 socket Bulk decoupling must be provided on the baseboard to handle la...

Страница 17: ...g signal integrity requirements as outlined in Table 2 19 The Dual Core Intel Xeon Processor 5200 Series utilizes differential clocks Table 2 1 contains processor core frequency to FSB multipliers and...

Страница 18: ...frequencies Individual processor VID values may be calibrated during manufacturing such that two devices at the same core frequency may have different default VID settings This is reflected by the VID...

Страница 19: ...core voltage Transitions above the specified VID are not permitted Table 2 12 includes VID step sizes and DC shift ranges Minimum and maximum voltages must be maintained as shown in Table 2 13 The VR...

Страница 20: ...1 0 1 2375 78 1 1 1 1 0 0 0 8625 3A 0 1 1 1 0 1 1 2500 76 1 1 1 0 1 1 0 8750 38 0 1 1 1 0 0 1 2625 74 1 1 1 0 1 0 0 8875 36 0 1 1 0 1 1 1 2750 72 1 1 1 0 0 1 0 9000 34 0 1 1 0 1 0 1 2875 70 1 1 1 0 0...

Страница 21: ...iate platform design guidelines For unused AGTL input or I O signals use pull up resistors of the same value as the on die termination resistors RTT For details see Table 2 18 TAP CMOS Asynchronous in...

Страница 22: ...nous data bus comes the need to specify two sets of timing parameters One set is for common clock signals whose timings are specified with respect to rising edge of BCLK0 ADS HIT HITM and so forth and...

Страница 23: ...NSE VCC_DIE_SENSE2 VCCPLL VID_SELECT VSS_DIE_SENSE VSS_DIE_SENSE2 VSS VTT VTT_OUT VTT_SEL Table 2 6 FSB Signal Groups Sheet 2 of 2 Signal Group Type Signals1 Table 2 7 AGTL Signal Description Table AG...

Страница 24: ...each signal may be required with each driving a different voltage level 2 10 Platform Environmental Control Interface PECI DC Specifications PECI is an Intel proprietary one wire interface that provi...

Страница 25: ...2 10 PECI DC Electrical Limits Symbol Definition and Conditions Min Max Units Notes1 Vin Input Voltage Range 0 150 VTT V Vhysteresis Hysteresis 0 1 VTT N A V Vn Negative edge threshold voltage 0 275 V...

Страница 26: ...2 Absolute Maximum and Minimum Ratings Table 2 11 specifies absolute maximum and minimum ratings only which lie outside the functional limits of the processor Only within specified operation limits ca...

Страница 27: ...formation is presented graphically in Figure 2 5 and Figure 2 6 The FSB clock signal group is detailed in Table 2 19 BSEL 2 0 and VID 6 1 signals are specified in Table 2 14 The DC specifications for...

Страница 28: ...Xeon Processor X5200 Series with multiple VID Launch FMB 90 A 4 5 6 9 ICC ICC for Dual Core Intel Xeon Processor E5200 Series with multiple VID Launch FMB 75 A 4 5 6 9 ICC ICC for Dual Core Intel Xeo...

Страница 29: ...s are for estimation purposes only See Section 2 13 1 for further details on FMB guidelines 7 This specification represents the total current for GTLREF_DATA and GTLREF_ADD 8 VTT must be provided via...

Страница 30: ...nd is not tested 15 This is the maximum total current drawn from the VTT plane by only one processor with RTT enabled This specification does not include the current coming from on board termination R...

Страница 31: ...Xeon Processor E5200 Series andDual Core Intel Xeon Processor X5200 Series and Dual Core Intel Xeon Processor L5200 Series VCC Static and Transient Tolerance ICC A VCC_Max V VCC_Typ V VCC_Min V Notes...

Страница 32: ...for socket load line guidelines and VR implementation Please refer to the appropriate platform design guide for details on VR implementation 4 ICC values greater than 75A are not applicable for the D...

Страница 33: ...0 VID 0 100 VID 0 120 VID 0 140 VID 0 160 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 Icc A Vcc V VCC Maximum VCC Typical VCC Minimum VID 0 000 VID 0 010 VID 0 020 VID 0 030 VID 0 040 VID 0...

Страница 34: ...asured at 0 31 VTT RON min 0 158 RTT RON typ 0 167 RTT RON max 0 175 RTT 6 GTLREF should be generated from VTT with a 1 tolerance resistor divider The VTT referred to in these specifications is the in...

Страница 35: ..._SENSE lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands Notes 1 VOS is the measured overshoot voltage 2 TOS is the measured time duration above VID 2 13 3 Die Voltage Validation Core volta...

Страница 36: ...e minimum and maximum specifications account for this resistor tolerance Refer to the appropriate platform design guidelines for implementation details The VTT referred to in these specifications is t...

Страница 37: ...ions simultaneously 9 VHavg can be measured directly using Vtop on Agilent and High on Tektronix oscilloscopes 10 For VIN between 0 V and VH 11 VCROSS is defined as the total variation of all crossing...

Страница 38: ...ng and Falling Edge Rates Crossing Voltage Threshold Region VH VL Overshoot Undershoot Ringback Margin Rising Edge Ringback Falling Edge Ringback BCLK0 BCLK1 Crossing Voltage Tp Tp T1 BCLK 1 0 period...

Страница 39: ...shown in Figure 3 1 include the following Integrated Heat Spreader IHS Thermal Interface Material TIM Processor Core die Package Substrate Landside capacitors Package Lands Note This drawing is not t...

Страница 40: ...ntial IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal Mechanical Design Guidelines Figure 3 2 Dual Core Intel Xeo...

Страница 41: ...41 Mechanical Specifications Figure 3 3 Dual Core Intel Xeon Processor 5200 Series Package Drawing Sheet 2 of 3...

Страница 42: ...Mechanical Specifications 42 Figure 3 4 Dual Core Intel Xeon Processor 5200 Series Package Drawing Sheet 3 of 3...

Страница 43: ...ization Loading limits are for the LGA771 socket 4 Dynamic compressive load applies to all board thickness 5 Dynamic loading is defined as an 11 ms duration average load superimposed on the static loa...

Страница 44: ...tion Specifications The Dual Core Intel Xeon Processor 5200 Series can be inserted and removed 15 times from an LGA771 socket which meets the criteria outlined in the LGA771 Socket Design Guidelines 3...

Страница 45: ...GROUP1LINE4 GROUP1LINE5 ATPO S N Legend GROUP1LINE1 GROUP1LINE2 GROUP1LINE3 GROUP1LINE4 GROUP1LINE5 Mark Text Production Mark 3400DP 6M 1600 Intel Xeon Proc SXXX COO i M 06 FPO Figure 3 6 Processor La...

Страница 46: ...21 22 23 24 25 26 27 28 29 30 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN 1 2 3 4 5 6...

Страница 47: ...put A22 AD6 Source Sync Input Output A23 AA5 Source Sync Input Output A24 AB5 Source Sync Input Output A25 AC5 Source Sync Input Output A26 AB4 Source Sync Input Output A27 AF5 Source Sync Input Outpu...

Страница 48: ...Output Table 4 1 Land Listing by Land Name Sheet 3 of 20 Pin Name Pin No Signal Buffer Type Direction D41 F20 Source Sync Input Output D42 E21 Source Sync Input Output D43 F21 Source Sync Input Outpu...

Страница 49: ...Sync Input Output REQ2 M6 Source Sync Input Output REQ3 K6 Source Sync Input Output REQ4 J6 Source Sync Input Output RESERVED AM6 RESERVED A13 RESERVED A20 RESERVED A23 RESERVED AC4 RESERVED AE4 RESER...

Страница 50: ...wer Other VCC AD29 Power Other VCC AD30 Power Other Table 4 1 Land Listing by Land Name Sheet 7 of 20 Pin Name Pin No Signal Buffer Type Direction VCC AD8 Power Other VCC AE11 Power Other VCC AE12 Pow...

Страница 51: ...4 Power Other Table 4 1 Land Listing by Land Name Sheet 9 of 20 Pin Name Pin No Signal Buffer Type Direction VCC AL15 Power Other VCC AL18 Power Other VCC AL19 Power Other VCC AL21 Power Other VCC AL2...

Страница 52: ...Power Other Table 4 1 Land Listing by Land Name Sheet 11 of 20 Pin Name Pin No Signal Buffer Type Direction VCC N27 Power Other VCC N28 Power Other VCC N29 Power Other VCC N30 Power Other VCC N8 Powe...

Страница 53: ...ower Other VSS AB27 Power Other VSS AB28 Power Other Table 4 1 Land Listing by Land Name Sheet 13 of 20 Pin Name Pin No Signal Buffer Type Direction VSS AB29 Power Other VSS AB30 Power Other VSS AB7 P...

Страница 54: ...27 Power Other Table 4 1 Land Listing by Land Name Sheet 15 of 20 Pin Name Pin No Signal Buffer Type Direction VSS AK28 Power Other VSS AK29 Power Other VSS AK30 Power Other VSS AK5 Power Other VSS AK...

Страница 55: ...Power Other Table 4 1 Land Listing by Land Name Sheet 17 of 20 Pin Name Pin No Signal Buffer Type Direction VSS G1 Power Other VSS H10 Power Other VSS H11 Power Other VSS H12 Power Other VSS H13 Powe...

Страница 56: ...3 Power Other VSS V30 Power Other Table 4 1 Land Listing by Land Name Sheet 19 of 20 Pin Name Pin No Signal Buffer Type Direction VSS V6 Power Other VSS V7 Power Other VSS W4 Power Other VSS W7 Power...

Страница 57: ...28 VSS Power Other AA29 VSS Power Other AA3 VSS Power Other AA30 VSS Power Other AA4 A21 Source Sync Input Output AA5 A23 Source Sync Input Output AA6 VSS Power Other AA7 VSS Power Other AA8 VCC Power...

Страница 58: ...ower Other Output Table 4 2 Land Listing by Land Number Sheet 3 of 20 Pin No Pin Name Signal Buffer Type Direction AE9 VCC Power Other AF1 TDO TAP Output AF10 VSS Power Other AF11 VCC Power Other AF12...

Страница 59: ...wer Other Table 4 2 Land Listing by Land Number Sheet 5 of 20 Pin No Pin Name Signal Buffer Type Direction AH27 VCC Power Other AH28 VCC Power Other AH29 VCC Power Other AH3 VSS Power Other AH30 VCC P...

Страница 60: ...4 2 Land Listing by Land Number Sheet 7 of 20 Pin No Pin Name Signal Buffer Type Direction AL18 VCC Power Other AL19 VCC Power Other AL2 PROCHOT Open Drain Output AL20 VSS Power Other AL21 VCC Power...

Страница 61: ...ction B10 D10 Source Sync Input Output B11 VSS Power Other B12 D13 Source Sync Input Output B13 RESERVED B14 VSS Power Other B15 D53 Source Sync Input Output B16 D55 Source Sync Input Output B17 VSS P...

Страница 62: ...D28 VTT Power Other Table 4 2 Land Listing by Land Number Sheet 11 of 20 Pin No Pin Name Signal Buffer Type Direction D29 VTT Power Other D3 VSS Power Other D30 VTT Power Other D4 HIT Common Clk Input...

Страница 63: ...e Sync Input Output G19 DSTBP2 Source Sync Input Output Table 4 2 Land Listing by Land Number Sheet 13 of 20 Pin No Pin Name Signal Buffer Type Direction G2 RESERVED G20 DSTBN2 Source Sync Input Outpu...

Страница 64: ...t Table 4 2 Land Listing by Land Number Sheet 15 of 20 Pin No Pin Name Signal Buffer Type Direction K2 VSS Power Other K23 VCC Power Other K24 VCC Power Other K25 VCC Power Other K26 VCC Power Other K...

Страница 65: ...P8 VCC Power Other R1 RESERVED Table 4 2 Land Listing by Land Number Sheet 17 of 20 Pin No Pin Name Signal Buffer Type Direction R2 VSS Power Other R23 VSS Power Other R24 VSS Power Other R25 VSS Powe...

Страница 66: ...C Power Other W24 VCC Power Other W25 VCC Power Other W26 VCC Power Other W27 VCC Power Other W28 VCC Power Other W29 VCC Power Other W3 RESERVED W30 VCC Power Other W4 VSS Power Other W5 A16 Source S...

Страница 67: ...O write instruction it must be valid along with the TRDY assertion of the corresponding I O write bus transaction 2 ADS I O ADS Address Strobe is asserted to indicate the validity of the transaction a...

Страница 68: ...BPM0 I O O I O O I O BPM 5 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters us...

Страница 69: ...for that 16 bit group 3 DBR O DBR is used only in systems where no debug port connector is implemented on the system board DBR is used by a debug port interposer so that an in target probe can drive...

Страница 70: ...3 of the Intel 64 and IA 32 Architectures Software Developer s Manual and the Intel Processor Identification and the CPUID Instruction application note 2 FORCEPR I The FORCEPR force power reduction i...

Страница 71: ...NMI becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous These signals must be software confi...

Страница 72: ...hese signals 3 RESET I Asserting the RESET signal resets all processors to known states and invalidates their internal caches without writing back any of their contents For a power on Reset RESET must...

Страница 73: ...PWRGOOD and is disabled on de assertion of PWRGOOD Once activated THERMTRIP remains latched until PWRGOOD is de asserted While the de assertion of the PWRGOOD signal will de assert THERMTRIP if the pr...

Страница 74: ...n the Dual Core Intel Xeon Processor 5200 Series package VSS_DIE_SENSE VSS_DIE_SENSE2 O VSS_DIE_SENSE and VSS_DIE_SENSE2 provides an isolated low impedance connection to the processor core power and g...

Страница 75: ...file see Table 6 1 and Figure 6 1 for the Dual Core Intel Xeon Processor E5200 Series Table 6 3 and Figure 6 2 for the Dual Core Intel Xeon Processor X5200 Series Table 6 6 and Figure 6 3 for the Dual...

Страница 76: ...olution that does not meet Thermal Profile B will violate the thermal specifications and may result in permanent damage to the processor Intel has developed these thermal profiles to allow customers t...

Страница 77: ...frequency requirements Notes 1 Please refer to Table 6 2 for discrete points that constitute the thermal profile 2 Implementation of the Dual Core Intel Xeon Processor E5200 Series Thermal Profile sh...

Страница 78: ...ilicon characterization 4 Power specifications are defined at all VIDs found in Table 2 12 The Dual Core Intel Xeon Processor X5200 Series may be shipped under multiple VIDs for each frequency 5 FMB o...

Страница 79: ...Mechanical Design Guidelines TMDG for system and environmental implementation details Figure 6 2 Dual Core Intel Xeon Processor X5200 Series Thermal Profiles A and B 40 45 50 55 60 65 70 0 10 20 30 4...

Страница 80: ...Power specifications are defined at all VIDs found in Table 2 12 The Dual Core Intel Xeon Processor L5200 Series may be shipped under multiple VIDs for each frequency 5 FMB or Flexible Motherboard gu...

Страница 81: ...of TCC activation and may incur measurable performance loss See Section 6 2 for details on TCC activation 3 Refer to the Dual Core Intel Xeon Processor 5200 Series Thermal Mechanical Design Guideline...

Страница 82: ...et the processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss See Section 6 2 for details on TCC activation 3 The Nominal Thermal Pr...

Страница 83: ...ncy 5 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements Notes 1 Dual Core Intel Xeon Processor L5215 Thermal Profile is representa...

Страница 84: ...es at the Short Term Thermal Profile for a duration longer than the limits specified in Note 4 above do not meet the processor thermal specifications and may result in permanent damage to the processo...

Страница 85: ...el Thermal Monitor 2 is not effective 6 2 1 1 Intel Thermal Monitor 1 The Intel Thermal Monitor 1 feature helps control the processor temperature by activating the Thermal Control Circuit TCC when the...

Страница 86: ...itor 2 This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor Intel Thermal Monitor 2 requires support for dynamic VID...

Страница 87: ...Transition of the VID code will occur first in order to insure proper operation once the processor reaches its normal operating frequency Refer to Figure 6 7 for an illustration of this ordering The P...

Страница 88: ...annot be adjusted based on experimental measurements of TCASE or PROCHOT 6 2 4 FORCEPR Signal The FORCEPR force power reduction input can be used by the platform to cause the Dual Core Intel Xeon Proc...

Страница 89: ...solutions based on PECI utilize a TCONTROL value stored in the processor IA32_TEMPERATURE_TARGET MSR The TCONTROL MSR uses the same offset temperature format as PECI though it contains no sign bit The...

Страница 90: ...The key items to take into account when settling on a fan control algorithm are the DTS sample rate whether the temperature filter is enabled how often the PECI host will poll the processor for temper...

Страница 91: ...ocessor operation during the time frame when reliable data is not available via PECI To protect platforms from potential operational or safety issues due to an abnormal condition on PECI the Host cont...

Страница 92: ...Thermal Specifications 92...

Страница 93: ...o the HALT state and Stop Grant state to reduce power consumption by stopping the clock to internal sections of the processor depending on each particular state See Figure 7 1 for a visual representat...

Страница 94: ...essor will process front side bus snoops and interrupts 7 2 2 2 Extended HALT State Extended HALT state is a low power state entered when all processor cores have executed the HALT or MWAIT instructio...

Страница 95: ...original value PEXTENDED_HALT Dual Core Intel Xeon Processor E5240 Extended HALT State Power 8 W 2 PEXTENDED_HALT Dual Core Intel Xeon Processor L5200 Series Extended HALT State Power 6 W 2 PEXTENDED...

Страница 96: ...y serviced when the processor returns to the Normal state Only one occurrence of each event will be recognized upon return to the Normal state While in Stop Grant state the processor will process snoo...

Страница 97: ...ility states within the Normal state see Figure 7 1 for the Stop Clock State Machine for supported P states Enhanced Intel SpeedStep Technology enables real time dynamic switching between frequency an...

Страница 98: ...Features 98...

Страница 99: ...nd lower TDPs will include an aluminum extruded 1U passive 3U active combination solution or an aluminum extruded 2U passive heatsink The 1U passive 3U active combination solution in the active fan co...

Страница 100: ...cifications 100 Figure 8 1 Boxed Dual Core Intel Xeon Processor 5200 Series 1U Passive 3U Active Combination Heat Sink With Removable Fan Figure 8 2 Boxed Dual Core Intel Xeon Processor 5200 Series 2U...

Страница 101: ...mechanical specifications of the boxed processor 8 2 1 Boxed Processor Heat Sink Dimensions CEK The boxed processor will be shipped with an unattached thermal solution Clearance is required around th...

Страница 102: ...Boxed Processor Specifications 102 Figure 8 4 Top Side Board Keepout Zones Part 1...

Страница 103: ...103 Boxed Processor Specifications Figure 8 5 Top Side Board Keepout Zones Part 2...

Страница 104: ...Boxed Processor Specifications 104 Figure 8 6 Bottom Side Board Keepout Zones...

Страница 105: ...105 Boxed Processor Specifications Figure 8 7 Board Mounting Hole Keepout Zones...

Страница 106: ...Boxed Processor Specifications 106 Figure 8 8 Volumetric Height Keep Ins...

Страница 107: ...107 Boxed Processor Specifications Figure 8 9 4 Pin Fan Cable Connector For Active CEK Heat Sink...

Страница 108: ...Boxed Processor Specifications 108 Figure 8 10 4 Pin Base Board Fan Header For Active CEK Heat Sink...

Страница 109: ...loads from the heat sink are transferred to the chassis pan via the stiff screws and standoffs The retention scheme reduces the risk of package pullout and solder joint failures All components of the...

Страница 110: ...1U Passive 3U Active Combination Heat Sink Solution 1U Rack Passive In the 1U configuration it is assumed that a chassis duct will be implemented to provide a minimum airflow of 15 cfm at 0 38 in H2O...

Страница 111: ...d by other system components Meeting the processor s temperature specification is the responsibility of the system integrator 8 3 2 3 2U Passive Heat Sink Solution 2U Rack or Pedestal In the 2U passiv...

Страница 112: ...Boxed Processor Specifications 112...

Страница 113: ...neral the information in this chapter may be used as a basis for including all run control tools in Dual Core Intel Xeon Processor 5200 Series based system designs including tools from vendors other t...

Страница 114: ...ke sure that the keepout volume remains unobstructed inside the system Note that it is possible that the keepout volume reserved for the LAI may include differerent requirements from the space normall...

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