Intel Core2 Extreme QX9000 Series, Техническое описание

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Datasheet 71
Land Listing and Signal Descriptions
SLP# Input
SLP# (Sleep), when asserted in Extended Stop Grant or Stop
Grant state, causes the processor to enter the Sleep state. In the
Sleep state, the processor stops providing internal clock signals to
all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts.
The processor will recognize only assertion of the RESET# signal,
deassertion of SLP#, and removal of the BCLK input while in Sleep
state. If SLP# is deasserted, the processor exits Sleep state and
returns to Extended Stop Grant or Stop Grant state, restarting its
internal clock signals to the bus and processor core units. If
DPSLP# is asserted while in the Sleep state, the processor will exit
the Sleep state and transition to the Deep Sleep state. Use of the
SLP# pin, and corresponding low power state, requires chipset
support and may not be available on all platforms.
NOTE: Some processors may not have the Sleep State enabled,
refer to the Specification Update for specific sku and
stepping guidance.
SMI# Input
SMI# (System Management Interrupt) is asserted asynchronously
by system logic. On accepting a System Management Interrupt,
the processor saves the current state and enter System
Management Mode (SMM). An SMI Acknowledge transaction is
issued, and the processor begins program execution from the
SMM handler.
If SMI# is asserted during the de-assertion of RESET#, the
processor will tri-state its outputs.
STPCLK# Input
STPCLK# (Stop Clock), when asserted, causes the processor to
enter a low power Stop-Grant state. The processor issues a Stop-
Grant Acknowledge transaction, and stops providing internal clock
signals to all processor core units except the FSB and APIC units.
The processor continues to snoop bus transactions and service
interrupts while in Stop-Grant state. When STPCLK# is de-
asserted, the processor restarts its internal clock to all units and
resumes execution. The assertion of STPCLK# has no effect on the
bus clock; STPCLK# is an asynchronous input.
TCK Input
TCK (Test Clock) provides the clock input for the processor Test
Bus (also known as the Test Access Port).
TDI, TDI_M Input
TDI and TDI_M (Test Data In) transfers serial test data into the
processor. TDI and TDI_M provide the serial input needed for JTAG
specification support. TDI connects to core 0. TDI_M connects to
core 1.
TDO, TDO_M Output
TDO and TDO_M (Test Data Out) transfers serial test data out of
the processor. TDO and TDO_M provide the serial output needed
for JTAG specification support. TDO connects to core 1. TDO_M
connects to core 0.
TESTHI[10,7:0] Input
TESTHI[10,7:0] must be connected to the processor’s appropriate
power source (refer to VTT_OUT_LEFT and VTT_OUT_RIGHT
signal description) through a resistor for proper processor
operation. See
Section 2.4 for more details.
Table 4-3. Signal Description (Sheet 8 of 10)
Name Type Description