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Electrical Specifications

Datasheet

2.7

Signaling Specifications

Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling

technology. This technology provides improved noise margins and reduced ringing

through low voltage swings and controlled edge rates.

Platforms implement a

termination voltage level for GTL+ signals defined as V

. Because platforms implement

separate power planes for each processor (and chipset), separate V

and V

supplies

are necessary. This configuration allows for improved noise tolerance as processor

frequency increases. Speed enhancements to data and address busses have caused

signal integrity considerations and platform design methods to become even more

critical than with previous processor families.

The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to

determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the

motherboard (see

Table 2-13

for GTLREF specifications). Termination resistors (R

) for

GTL+ signals are provided on the processor silicon and are terminated to V

. Intel

chipsets will also provide on-die termination; thus, eliminating the need to terminate

the bus on the motherboard for most GTL+ signals.

2.7.1

FSB Signal Groups

The front side bus signals have been combined into groups by buffer type. GTL+ input

signals have differential input buffers, which use GTLREF[3:0] as a reference level. In

this document, the term “GTL+ Input” refers to the GTL+ input group as well as the

GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output

group as well as the GTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify

two sets of timing parameters. One set is for common clock signals which are

dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second

set is for the source synchronous signals which are relative to their respective strobe

lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are

still present (A20M#, IGNNE#, etc.) and can become active at any time during the

clock cycle.

Table 2-6

identifies which signals are common clock, source synchronous,

and asynchronous.

Table 2-6.

FSB Signal Groups (Sheet 1 of 2)

Signal Group

Type

Signals

GTL+ Common
Clock Input

Synchronous to
BCLK[1:0]

BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY#

GTL+ Common
Clock I/O

Synchronous to
BCLK[1:0]

ADS#, BNR#, BPM[5:0]#, BPMb[3:0]#, BR0#

, DBSY#,

DRDY#, HIT#, HITM#, LOCK#

GTL+ Source
Synchronous I/O

Synchronous to
assoc. strobe

Signals

Associated Strobe

REQ[4:0]#, A[16:3]#

ADSTB0#

A[35:17]#

ADSTB1#

D[15:0]#, DBI0#

DSTBP0#, DSTBN0#

D[31:16]#, DBI1#

DSTBP1#, DSTBN1#

D[47:32]#, DBI2#

DSTBP2#, DSTBN2#

D[63:48]#, DBI3#

DSTBP3#, DSTBN3#

Содержание Core2 Extreme QX9000 Series

Страница 1: ...ocument Number 318726 010 Intel Core 2 Extreme Processor QX9000Δ Series Intel Core 2 Quad Processor Q9000Δ Q9000SΔ Q8000Δ and Q8000SΔ Series Datasheet on 45 nm process in the 775 land package August 2009 ...

Страница 2: ... products processor_number for details Intel 64 requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 Processor will not operate including 32 bit operation without an Intel 64 enabled BIOS Performance will vary depending on your hardware and software configurations See http www intel com info em64t for more information includ...

Страница 3: ...face PECI DC Specifications 29 2 7 3 2 GTL Front Side Bus Specifications 30 2 8 Clock Specifications 31 2 8 1 Front Side Bus Clock BCLK 1 0 and Processor Clocking 31 2 8 2 FSB Frequency Select Signals BSEL 2 0 32 2 8 3 Phase Lock Loop PLL and Filter 32 2 8 4 BCLK 1 0 Specifications 32 3 Package Mechanical Specifications 35 3 1 Package Mechanical Drawing 35 3 2 Processor Component Keep Out Zones 39...

Страница 4: ...d Stop Grant Snoop State 92 6 2 4 1 HALT Snoop State Stop Grant Snoop State 92 6 2 4 2 Extended HALT Snoop State Extended Stop Grant Snoop State 92 6 2 5 Sleep State 92 6 2 6 Deep Sleep State 93 6 2 7 Deeper Sleep State 93 6 2 8 Enhanced Intel SpeedStep Technology 94 6 3 Processor Power Status Indicator PSI Signal 94 7 Boxed Processor Specifications 95 7 1 Introduction 95 7 2 Mechanical Specificat...

Страница 5: ... Intel Core 2 Quad Processor Q9000S and Q8000S Series Thermal Profile 81 5 5 Case Temperature TC Measurement Location 82 5 6 Thermal Monitor 2 Frequency and Voltage Ordering 84 5 7 Conceptual Fan Control Diagram on PECI Based Platforms 86 6 1 Processor Low Power State Machine 90 7 1 Mechanical Representation of the Boxed Processor 95 7 2 Space Requirements for the Boxed Processor side view 96 7 3 ...

Страница 6: ...16 Front Side Bus Differential BCLK Specifications 32 2 17 FSB Differential Clock Specifications 1600 MHz FSB 33 2 18 FSB Differential Clock Specifications 1333 MHz FSB 33 3 1 Processor Loading Specifications 39 3 2 Package Handling Guidelines 39 3 3 Processor Materials 40 4 1 Alphabetical Land Assignments 46 4 2 Numerical Land Assignment 55 4 3 Signal Description 64 5 1 Processor Thermal Specific...

Страница 7: ...2 3 6 2 4 6 2 5 6 2 6 6 2 7 and 6 3 Updated FSB termination voltage in Table 2 3 August 2008 005 Added Intel Core 2 Quad processor Q8200 August 2008 006 Added Intel Core 2 Quad processor Q8300 December 2008 007 Added Intel Core 2 Quad processor Q9000S and Q8000S series Q9550S Q9400S and Q8200S January 2009 008 Added Intel Core 2 Quad processors Q8400 and Q8400S April 2009 009 Corrected list of Int...

Страница 8: ...8 Datasheet ...

Страница 9: ...uad processor Q9550S Q9505S and Q9400S Available at 2 66 GHz and 2 33 GHz Intel Core 2 Quad processor Q8400S and Q8200S FSB frequency at 1333 MHz Intel Core 2 Extreme processor QX9650 Intel Core 2 Quad Q9000 Q9000S Q8000 and Q8000S series only FSB frequency at 1600 MHz Intel Core 2 Extreme processor QX9770 only Enhanced Intel SpeedStep Technology Supports Intel 64Φ architecture Supports Intel Virt...

Страница 10: ...tware to improve on software only solutions The Intel Core 2 Quad processor Q9000 and Q9000S series support Intel Trusted Execution Technology Intel TXT Intel TXT is a key element in Intel s safer computing initiative that defines a set of hardware enhancements that operate with an Intel TXT enabled operating system to help protect against software based attacks It creates a hardware foundation th...

Страница 11: ...ocessor is based on 45 nm process technology The processor features the Intel Advanced Smart Cache a shared multi core optimized cache that significantly reduces latency to frequently used data The processors feature 1600 MHz and 1333 MHz front side bus FSB frequencies The processors also feature two independent but shared 12 MB of L2 cache 2x6M two independent but shared 8 MB of L2 cache 2x4M two...

Страница 12: ...000 Series Quad core processor in the FC LGA8 package with two 4 MB L2 caches or two 2 MB L2 caches Intel Core 2 Quad processor Q9000S series Low power Quad core processor in the FC LGA8 package with two 6 MB L2 caches or two 3 MB L2 caches Intel Core 2 Quad Processor Q8000S Series Low power Quad core processor in the FC LGA8 package with two 4 MB L2 caches or two 2 MB L2 caches caches Processor F...

Страница 13: ...stems and applications written to take advantage of Intel 64 architecture Further details on Intel 64 architecture and programming model can be found in the Software Developer Guide at http developer intel com technology 64bitextensions Enhanced Intel SpeedStep Technology Enhanced Intel SpeedStep Technology allows trade offs to be made between performance and power consumptions based on processor ...

Страница 14: ...ssor QX6800 and Intel Core 2 Extreme Processor QX9770 Thermal and Mechanical Design Guidelines http www intel com design processor designex 316854 htm Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket http www intel com design processor applnots 313214 htm Balanced Technology Extended BTX System Design Guide www formfactors org LGA775 Socket Mecha...

Страница 15: ...ming out of an idle condition Similarly they act as a storage well for current when entering an idle condition from a running condition The motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications listed in Table 2 3 Failure to do so can result in timing violations or reduced lifetime of the component 2 2 1 VCC Decoupling VCC regulator sol...

Страница 16: ...el Core 2 Extreme Processor QX9000 Series and Intel Core 2 Quad Processor Q9000 Q9000S Q8000 and Q8000S Series Specification Update for further details on specific valid core frequency and VID values of the processor Note that this differs from the VID employed by the processor during a power management event Thermal Monitor 2 Enhanced Intel SpeedStep technology or Extended HALT State The processo...

Страница 17: ... 0 1 3875 1 0 0 0 0 0 0 0 0 8125 0 0 1 0 0 1 1 0 1 375 1 0 0 0 0 0 1 0 0 8 0 0 1 0 1 0 0 0 1 3625 1 0 0 0 0 1 0 0 0 7875 0 0 1 0 1 0 1 0 1 35 1 0 0 0 0 1 1 0 0 775 0 0 1 0 1 1 0 0 1 3375 1 0 0 0 1 0 0 0 0 7625 0 0 1 0 1 1 1 0 1 325 1 0 0 0 1 0 1 0 0 75 0 0 1 1 0 0 0 0 1 3125 1 0 0 0 1 1 0 0 0 7375 0 0 1 1 0 0 1 0 1 3 1 0 0 0 1 1 1 0 0 725 0 0 1 1 0 1 0 0 1 2875 1 0 0 1 0 0 0 0 0 7125 0 0 1 1 0 1 1...

Страница 18: ... signals do not include on die termination Inputs and used outputs must be terminated on the motherboard Unused outputs may be terminated on the motherboard or left unconnected Note that leaving unused outputs unterminated may interfere with some TAP functions complicate debug probing and prevent boundary scan testing All TESTHI 10 7 0 lands should be individually connected to VTT via a pull up re...

Страница 19: ...imits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields NOTES 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Exces...

Страница 20: ..._VR_CONFIG_05B 3 00 GHz 12 MB Cache V Processor Number Q9650 Q9550 Q9550S Q9505 Q9505S Q9450 Q9400 Q9400S Q9300 Q8400 Q8300 Q8200 Q8400S Q8200S VCC for 775_VR_CONFIG_05A 3 0 GHz 12 MB Cache 2 83 GHz 12 MB Cache 2 83 GHz 12 MB Cache 2 83 GHz 8 MB Cache 2 83 GHz 8 MB Cache 2 66 GHz 12 MB Cache 2 66 GHz 6 MB Cache 2 66 GHz 6 MB Cache 2 50 GHz 6 MB Cache 2 66 GHz 8 MB Cache 2 50 GHz 4 MB Cache 2 33 GH...

Страница 21: ...ds at the socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe ICC Processor Number QX9770 3 20 GHz 12 MB Cache 140 A 6 Processor Number QX9650 ICC for 775_VR_CONFIG_05B 3 00 GHz 12 MB Cache 125 A Processor Number Q9650 Q9550 Q9550S Q9505 Q9505S Q9450 Q9400 Q9400S Q9300 Q8400 Q8300 Q8200 Q8400S Q8200S ICC for 775_VR_CONFIG_05A 3 0 GHz 12 MB Cache 2 83 GHz 12 MB Cache 2 83 GHz 12 MB Ca...

Страница 22: ...d on VCC_MAX loadline Refer to Figure 2 1 for details 7 VTT must be provided via a separate voltage source and not be connected to VCC This specification is measured at the land 8 Baseboard bandwidth is limited to 20 MHz 9 This is the maximum total current drawn from the VTT plane by only the processor This specification does not include the current coming from on board termination RTT through the...

Страница 23: ...specification is required to ensure reliable processor operation Table 2 4 VCC Static and Transient Tolerance ICC A Voltage Deviation from VID Setting V 1 2 3 4 Maximum Voltage 1 30 mΩ Typical Voltage 1 38 mΩ Minimum Voltage 1 45 mΩ 0 0 000 0 019 0 038 5 0 007 0 026 0 045 10 0 013 0 033 0 053 15 0 020 0 040 0 060 20 0 026 0 047 0 067 25 0 033 0 053 0 074 30 0 039 0 060 0 082 35 0 046 0 067 0 089 4...

Страница 24: ...ds Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands Refer to the Voltage Regulator Design Guide for socket loadline guidelines and VR implementation details Figure 2 1 VCC Static and Transient Tolerance VID 0 000 VID 0 013 VID 0 025 VID 0 038 VID 0 050 VID 0 063 VID 0 075 VID 0 088 VID 0 100 VID 0 113 VID 0 125 VID 0 138 VID 0 150 VID 0 163 ...

Страница 25: ...ge Validation Overshoot events on processor must meet the specifications in Table 2 5 when measured across the VCC_SENSE and VSS_SENSE lands Overshoot events that are 10 ns in duration may be ignored These measurements of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to 100 MHz bandwidth limit Table 2 5 VCC Overshoot Specifications...

Страница 26: ...SB Signal Groups The front side bus signals have been combined into groups by buffer type GTL input signals have differential input buffers which use GTLREF 3 0 as a reference level In this document the term GTL Input refers to the GTL input group as well as the GTL I O group when receiving Similarly GTL Output refers to the GTL output group as well as the GTL I O group when driving With the imple...

Страница 27: ...n Input Output PROCHOT 4 FSB Clock Clock BCLK 1 0 ITP_CLK 1 0 2 Power Other VCC VTT VCCA VCCIOPLL VCCPLL VSS VSSA GTLREF 3 0 COMP 8 3 0 RESERVED TESTHI 10 7 0 VCC_SENSE VCC_MB_REGULATION VSS_SENSE VSS_MB_REGULATION DBR 2 VTT_OUT_LEFT VTT_OUT_RIGHT VTT_SEL FCx PECI MSID 1 0 Table 2 6 FSB Signal Groups Sheet 2 of 2 Signal Group Type Signals1 Table 2 7 Signal Characteristics Signals with RTT Signals ...

Страница 28: ...a logical low value 3 VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value 4 VIH and VOH may experience excursions above VTT 5 The VTT referred to in these specifications is the instantaneous VTT 6 Leakage to VSS with land held at VTT 7 Leakage to VTT with land held at 300 mV NOTES 1 Unless otherwise noted all specifications in this table apply ...

Страница 29: ...l processors chipsets and external thermal monitoring devices The processor contains Digital Thermal Sensors DTS distributed throughout die These sensors are implemented as analog to digital converters calibrated at the factory for reasonable accuracy to provide a digital representation of relative processor temperature PECI provides an interface to relay the highest DTS temperature within a die t...

Страница 30: ...trical Limits Symbol Definition and Conditions Min Max Units Notes1 NOTES 1 VTT supplies the PECI interface PECI behavior does not affect VTT min max specifications Refer to Table 2 3 for VTT specifications Vin Input Voltage Range 0 15 VTT V Vhysteresis Hysteresis 0 1 VTT V 2 2 The leakage specification applies to powered devices on the PECI bus Vn Negative edge threshold voltage 0 275 VTT 0 500 V...

Страница 31: ...mation on the processor clocking contact your Intel field representative NOTES 1 Individual processors operate only at or below the rated frequency 2 Listed frequencies are not necessarily committed production frequencies Table 2 14 Core Frequency to FSB Multiplier Configuration Multiplication of System Core Frequency to FSB Frequency Core Frequency 333 MHz BCLK 1333 MHz FSB Core Frequency 400 MHz...

Страница 32: ...d for the PLL Refer to Table 2 3 for DC specifications 2 8 4 BCLK 1 0 Specifications NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1 3 Steady state voltage not including overshoot or undershoot 4 Overshoot is defined as t...

Страница 33: ...here is the average period A given period may vary from this specification as governed by the period stability specification T2 Min period specification is based on 300 PPM deviation from a 3 ns period Max period specification is based on the summation of 300 PPM deviation from a 3 ns period and a 0 5 maximum variance due to spread spectrum clocking 3 In this context period stability is defined as...

Страница 34: ...ck Falling Edge Ringback BCLK0 BCLK1 Tph Tpl Tp Tp T1 BCLK 1 0 period T2 BCLK 1 0 period stability not shown Tph T3 BCLK 1 0 pulse high time Tpl T4 BCLK 1 0 pulse low time T5 BCLK 1 0 rise time through the threshold region T6 BCLK 1 0 fall time through the threshold region VCROSS ABS VCROSS ABS 150 mV 150 mV 0 0V 0 0V Slew_rise 150mV 150mV V_swing Slew _fall Diff T5 BCLK 1 0 rise and fall time thr...

Страница 35: ...rated Heat Spreader IHS Thermal Interface Material TIM Processor core die Package substrate Capacitors NOTE 1 Socket and motherboard are included for reference and are not part of processor package 3 1 Package Mechanical Drawing The package mechanical drawings are shown in Figure 3 2 and Figure 3 3 The drawings include dimensions necessary to design a thermal solution for the processor These dimen...

Страница 36: ...Package Mechanical Specifications 36 Datasheet Figure 3 2 Processor Package Drawing Sheet 1 of 3 ...

Страница 37: ...Datasheet 37 Package Mechanical Specifications Figure 3 3 Processor Package Drawing Sheet 2 of 3 ...

Страница 38: ...Package Mechanical Specifications 38 Datasheet Figure 3 4 Processor Package Drawing Sheet 3 of 3 ...

Страница 39: ...ormal to the processor IHS 2 This is the maximum force that can be applied by a heatsink retention clip The clip must also provide the minimum specified load on the processor package 3 These specifications are based on limited testing for design characterization Loading limits are for the package only and do not include the limits of the processor socket 4 Dynamic loading is defined as an 11 ms du...

Страница 40: ...ed in the package 3 7 Processor Materials Table 3 3 lists some of the package components and associated materials 3 8 Processor Markings Figure 3 5 and Figure 3 6 show the topside markings on the processor This diagram is to aid in the identification of the processor Table 3 3 Processor Materials Component Material Integrated Heat Spreader IHS Nickel Plated Copper Substrate Fiber Reinforced Resin ...

Страница 41: ... 41 Package Mechanical Specifications Figure 3 6 Processor Top Side Markings Example Intel Core 2 Quad Processor Q9000 Series ATPO S N INTEL 06 Q9550 INTEL CORE 2 Quad SLAN3 XXXX 2 83GHZ 2M 1333 05A FPO e4 M e4 ...

Страница 42: ...nates and Quadrants Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Socket 775 Quadrants Top View VCC VSS VTT Clocks Da...

Страница 43: ...ns the land listings for the processor The land out footprint is shown in Figure 4 1 and Figure 4 2 These figures represent the land out arranged by land number and they show the physical location of each signal on the package land array top view Table 4 1 is a listing of all processor lands ordered alphabetically by land signal name Table 4 2 is also a listing of all processor lands the ordering ...

Страница 44: ...Y VCC VCC VCC VCC VCC VCC VCC VCC W VCC VCC VCC VCC VCC VCC VCC VCC V VSS VSS VSS VSS VSS VSS VSS VSS U VCC VCC VCC VCC VCC VCC VCC VCC T VCC VCC VCC VCC VCC VCC VCC VCC R VSS VSS VSS VSS VSS VSS VSS VSS P VSS VSS VSS VSS VSS VSS VSS VSS N VCC VCC VCC VCC VCC VCC VCC VCC M VCC VCC VCC VCC VCC VCC VCC VCC L VSS VSS VSS VSS VSS VSS VSS VSS K VCC VCC VCC VCC VCC VCC VCC VCC J VCC VCC VCC VCC VCC VCC ...

Страница 45: ...3 A21 VSS FC39 VTT_OUT_ RIGHT AA VCC VSS A19 VSS A20 PSI VSS FC0 BOOT SELECT Y VCC VSS A18 A16 VSS TESTHI1 TDI_M MSID0 W VCC VSS VSS A14 A15 VSS RSVD MSID1 V VCC VSS A10 A12 A13 FC30 FC29 TDO_M U VCC VSS VSS A9 A11 VSS DPRSTP COMP1 T VCC VSS ADSTB0 VSS A8 FERR PBE VSS COMP3 R VCC VSS A4 RSVD VSS INIT SMI DPSLP P VCC VSS VSS RSVD RSVD VSS IGNNE PWRGOOD N VCC VSS REQ2 A5 A7 STPCLK THER MTRIP VSS M V...

Страница 46: ... BPM2 AD2 Common Clock Input Output BPM3 AG2 Common Clock Input Output BPM4 AF2 Common Clock Input Output BPM5 AG3 Common Clock Input Output BPMb0 G1 Common Clock Input Output BPMb1 C9 Common Clock Input Output BPMb2 G4 Common Clock Input Output BPMb3 G3 Common Clock Input Output BPRI G8 Common Clock Input BR0 F3 Common Clock Input Output BSEL0 G29 Asynch CMOS Output BSEL1 H30 Asynch CMOS Output B...

Страница 47: ...n Clock Input DPRSTP T2 Asynch CMOS Input DPSLP P1 Asynch CMOS Input DRDY C1 Common Clock Input Output DSTBN0 C8 Source Synch Input Output DSTBN1 G12 Source Synch Input Output DSTBN2 G20 Source Synch Input Output DSTBN3 A16 Source Synch Input Output Table 4 1 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction DSTBP0 B9 Source Synch Input Output DSTBP1 E12 Source Synch Input ...

Страница 48: ...25 Power Other Input TESTHI4 G27 Power Other Input Table 4 1 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction TESTHI5 G26 Power Other Input TESTHI6 G24 Power Other Input TESTHI7 F24 Power Other Input THERMTRIP M2 Asynch CMOS Output TMS AC1 TAP Input TRDY E3 Common Clock Input TRST AG1 TAP Input VCC AA8 Power Other VCC AB8 Power Other VCC AC23 Power Other VCC AC24 Power Oth...

Страница 49: ... VCC AJ9 Power Other VCC AK11 Power Other Table 4 1 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VCC AK12 Power Other VCC AK14 Power Other VCC AK15 Power Other VCC AK18 Power Other VCC AK19 Power Other VCC AK21 Power Other VCC AK22 Power Other VCC AK25 Power Other VCC AK26 Power Other VCC AK8 Power Other VCC AK9 Power Other VCC AL11 Power Other VCC AL12 Power Other VCC...

Страница 50: ... Other VCC M29 Power Other VCC M30 Power Other Table 4 1 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VCC M8 Power Other VCC N23 Power Other VCC N24 Power Other VCC N25 Power Other VCC N26 Power Other VCC N27 Power Other VCC N28 Power Other VCC N29 Power Other VCC N30 Power Other VCC N8 Power Other VCC P8 Power Other VCC R8 Power Other VCC T23 Power Other VCC T24 Power...

Страница 51: ... AA30 Power Other VSS AA6 Power Other VSS AA7 Power Other VSS AB1 Power Other Table 4 1 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VSS AB23 Power Other VSS AB24 Power Other VSS AB25 Power Other VSS AB26 Power Other VSS AB27 Power Other VSS AB28 Power Other VSS AB29 Power Other VSS AB30 Power Other VSS AB7 Power Other VSS AC3 Power Other VSS AC6 Power Other VSS AC7 Po...

Страница 52: ...r Other VSS AK7 Power Other VSS AL10 Power Other Table 4 1 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VSS AL13 Power Other VSS AL16 Power Other VSS AL17 Power Other VSS AL20 Power Other VSS AL23 Power Other VSS AL24 Power Other VSS AL27 Power Other VSS AL28 Power Other VSS AL7 Power Other VSS AM1 Power Other VSS AM10 Power Other VSS AM13 Power Other VSS AM16 Power Ot...

Страница 53: ...ther VSS K5 Power Other VSS K7 Power Other Table 4 1 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VSS L23 Power Other VSS L24 Power Other VSS L25 Power Other VSS L26 Power Other VSS L27 Power Other VSS L28 Power Other VSS L29 Power Other VSS L3 Power Other VSS L30 Power Other VSS L6 Power Other VSS L7 Power Other VSS M1 Power Other VSS M7 Power Other VSS N3 Power Other...

Страница 54: ...her VTT B30 Power Other VTT A25 Power Other Table 4 1 Alphabetical Land Assignments Land Name Land Signal Buffer Type Direction VTT A26 Power Other VTT A27 Power Other VTT A28 Power Other VTT A29 Power Other VTT A30 Power Other VTT C25 Power Other VTT C26 Power Other VTT C27 Power Other VTT C28 Power Other VTT C29 Power Other VTT C30 Power Other VTT D25 Power Other VTT D26 Power Other VTT D27 Powe...

Страница 55: ...r AC7 VSS Power Other AC8 VCC Power Other AC23 VCC Power Other AC24 VCC Power Other AC25 VCC Power Other AC26 VCC Power Other AC27 VCC Power Other AC28 VCC Power Other AC29 VCC Power Other AC30 VCC Power Other AD1 TDI TAP Input AD2 BPM2 Common Clock Input Output AD3 FC36 Power Other AD4 VSS Power Other AD5 ADSTB1 Source Synch Input Output AD6 A22 Source Synch Input Output AD7 VSS Power Other AD8 V...

Страница 56: ...her AG10 VSS Power Other AG11 VCC Power Other AG12 VCC Power Other AG13 VSS Power Other Table 4 2 Numerical Land Assignment Land Land Name Signal Buffer Type Direction AG14 VCC Power Other AG15 VCC Power Other AG16 VSS Power Other AG17 VSS Power Other AG18 VCC Power Other AG19 VCC Power Other AG20 VSS Power Other AG21 VCC Power Other AG22 VCC Power Other AG23 VSS Power Other AG24 VSS Power Other A...

Страница 57: ...S Power Other AK14 VCC Power Other AK15 VCC Power Other Table 4 2 Numerical Land Assignment Land Land Name Signal Buffer Type Direction AK16 VSS Power Other AK17 VSS Power Other AK18 VCC Power Other AK19 VCC Power Other AK20 VSS Power Other AK21 VCC Power Other AK22 VCC Power Other AK23 VSS Power Other AK24 VSS Power Other AK25 VCC Power Other AK26 VCC Power Other AK27 VSS Power Other AK28 VSS Pow...

Страница 58: ...SS Power Other Table 4 2 Numerical Land Assignment Land Land Name Signal Buffer Type Direction AN17 VSS Power Other AN18 VCC Power Other AN19 VCC Power Other AN20 VSS Power Other AN21 VCC Power Other AN22 VCC Power Other AN23 VSS Power Other AN24 VSS Power Other AN25 VCC Power Other AN26 VCC Power Other AN27 VSS Power Other AN28 VSS Power Other AN29 VCC Power Other AN30 VCC Power Other A2 VSS Powe...

Страница 59: ...D51 Source Synch Input Output C16 VSS Power Other C17 DSTBP3 Source Synch Input Output C18 D54 Source Synch Input Output C19 VSS Power Other Table 4 2 Numerical Land Assignment Land Land Name Signal Buffer Type Direction C20 DBI3 Source Synch Input Output C21 D58 Source Synch Input Output C22 VSS Power Other C23 VCCIOPLL Power Other C24 VSS Power Other C25 VTT Power Other C26 VTT Power Other C27 V...

Страница 60: ...ble 4 2 Numerical Land Assignment Land Land Name Signal Buffer Type Direction F25 TESTHI2 Power Other Input F26 TESTHI0 Power Other Input F27 VTT_SEL Power Other Output F28 BCLK0 Clock Input F29 RESERVED G1 BPMb0 Common Clock Input Output G2 COMP2 Power Other Input G3 BPMb3 Common Clock Input Output G4 BPMb2 Common Clock Input Output G5 PECI Power Other Input Output G6 RESERVED G7 DEFER Common Clo...

Страница 61: ...able 4 2 Numerical Land Assignment Land Land Name Signal Buffer Type Direction J27 VCC Power Other J28 VCC Power Other J29 VCC Power Other J30 VCC Power Other K1 LINT0 Asynch CMOS Input K2 VSS Power Other K3 A20M Asynch CMOS Input K4 REQ0 Source Synch Input Output K5 VSS Power Other K6 REQ3 Source Synch Input Output K7 VSS Power Other K8 VCC Power Other K23 VCC Power Other K24 VCC Power Other K25 ...

Страница 62: ...r Other R8 VCC Power Other Table 4 2 Numerical Land Assignment Land Land Name Signal Buffer Type Direction R23 VSS Power Other R24 VSS Power Other R25 VSS Power Other R26 VSS Power Other R27 VSS Power Other R28 VSS Power Other R29 VSS Power Other R30 VSS Power Other T1 COMP1 Power Other Input T2 DPRSTP Asynch CMOS Input T3 VSS Power Other T4 A11 Source Synch Input Output T5 A09 Source Synch Input ...

Страница 63: ...wer Other W24 VCC Power Other W25 VCC Power Other Table 4 2 Numerical Land Assignment Land Land Name Signal Buffer Type Direction W26 VCC Power Other W27 VCC Power Other W28 VCC Power Other W29 VCC Power Other W30 VCC Power Other Y1 FC0 BOOTSELECT Power Other Y2 VSS Power Other Y3 PSI Asynch CMOS Output Y4 A20 Source Synch Input Output Y5 VSS Power Other Y6 A19 Source Synch Input Output Y7 VSS Pow...

Страница 64: ...orted in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction ADS Input Output ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 35 3 and REQ 4 0 signals All bus agents observe t...

Страница 65: ...essor FSB agents Observing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by de asserting BPRI BR0 Input Output BR0 drives the BREQ0 signal in the system and is used by the processor to ...

Страница 66: ...the D 63 0 signals The DBI 3 0 signals are activated when the data on the data bus is inverted If more than half the data bits within a 16 bit group would have been asserted electrically low the bus agent may invert the data bus signals for that particular sub phase for that 16 bit group DBR Output DBR Debug Reset is used only in processor systems where no debug port is implemented on the system b...

Страница 67: ...state requires chipset support and may not be available on all platforms NOTE Some processors may not have the Deep Sleep State enabled refer to the Specification Update for specific sku and stepping guidance DRDY Input Output DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY may be de asserted to i...

Страница 68: ...her IERR Output IERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor FSB This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until the assertion of RESET This signal does not have on die termination ...

Страница 69: ...first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the processor FSB it will wait until it observes LOCK de asserted This enables symmetric agents to retain ownership of the processor FSB throughout the bus locked operation and ensure the atomicity of lock MSID 1 0 Output On the processor these signals are not connected on the pa...

Страница 70: ...rocessor to a known state and invalidates its internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least one millisecond after VCC and BCLK have reached their proper specifications On observing active RESET all FSB agents will de assert their outputs within two clocks RESET must not be kept asserted for more than 10 ms while PWRGOOD is asser...

Страница 71: ...ins program execution from the SMM handler If SMI is asserted during the de assertion of RESET the processor will tri state its outputs STPCLK Input STPCLK Stop Clock when asserted causes the processor to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the FSB and APIC units T...

Страница 72: ...t is a JTAG specification support signal used by debug tools TRDY Input TRDY Target Ready is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins lands of all FSB agents TRST Input TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset VCC Input VCC are the powe...

Страница 73: ...cy platforms where this land is connected to VSS VSS Input VSS are the ground pins for the processor and should be connected to the system ground plane VSSA Input VSSA provides isolated ground for internal PLLs on previous generation processors It may be left as a No Connect on boards supporting the processor VSS_SENSE Output VSS_SENSE is an isolated low impedance connection to processor core VSS ...

Страница 74: ...Land Listing and Signal Descriptions 74 Datasheet ...

Страница 75: ...n Power TDP value listed per frequency in Table 5 1 Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system For more details on thermal solution design refer to the appropriate Thermal and Mechanical Design Guidelines See Section 1 2 The processor uses a methodology for managing processor temperatures which is inte...

Страница 76: ...al solution design targets The TDP is not the maximum power that the processor can dissipate 4 This table shows the maximum TDP for a given frequency range Individual processors may have a lower TDP Therefore the maximum TC will vary depending on the TDP of the individual processor Refer to thermal profile figure and associated table for the allowed combinations of power and TC 5 775_VR_CONFIG_05 ...

Страница 77: ...0 39 1 44 43 5 78 47 9 112 52 4 12 39 4 46 43 8 80 48 2 114 52 6 14 39 6 48 44 0 82 48 5 116 52 9 16 39 9 50 44 3 84 48 7 118 53 1 18 40 1 52 44 6 86 49 0 120 53 4 20 40 4 54 44 8 88 49 2 122 53 7 22 40 7 56 45 1 90 49 5 124 53 9 24 40 9 58 45 3 92 49 8 126 54 2 26 41 2 60 45 6 94 50 0 128 54 4 28 41 4 62 45 9 96 50 3 130 54 7 30 41 7 64 46 1 98 50 5 132 55 0 32 42 0 66 46 4 100 50 8 134 55 2 136 ...

Страница 78: ... 1 44 49 9 78 55 7 112 61 4 12 44 4 46 50 2 80 56 0 114 61 8 14 44 8 48 50 6 82 56 3 116 62 1 16 45 1 50 50 9 84 56 7 118 62 5 18 45 5 52 51 2 86 57 0 120 62 8 20 45 8 54 51 6 88 57 4 122 63 1 22 46 1 56 51 9 90 57 7 124 63 5 24 46 5 58 52 3 92 58 0 126 63 8 26 46 8 60 52 6 94 58 4 128 64 2 28 47 2 62 52 9 96 58 7 130 64 5 30 47 5 64 53 3 98 59 1 32 47 8 66 53 6 100 59 4 Figure 5 2 Intel Core 2 Ex...

Страница 79: ...30 53 2 56 60 5 82 67 8 6 46 5 32 53 8 58 61 0 84 68 3 8 47 0 34 54 3 60 61 6 86 68 9 10 47 6 36 54 9 62 62 2 88 69 4 12 48 2 38 55 4 64 62 7 90 70 0 14 48 7 40 56 0 66 63 3 92 70 6 16 49 3 42 56 6 68 63 8 94 71 1 18 49 8 44 57 1 70 64 4 95 71 4 20 50 4 46 57 7 72 65 0 22 51 0 48 58 2 74 65 5 24 51 5 50 58 8 76 66 1 Figure 5 3 Intel Core 2 Quad Processor Q9000 and Q8000 Series Thermal Profile y 0 ...

Страница 80: ...c C 0 49 6 18 57 0 36 64 4 54 71 7 2 50 4 20 57 8 38 65 2 56 72 6 4 51 2 22 58 6 40 66 0 58 73 4 6 52 1 24 59 4 42 66 8 60 74 2 8 52 9 26 60 3 44 67 6 62 75 0 10 53 7 28 61 1 46 68 5 64 75 8 12 54 5 30 61 9 48 69 3 65 76 3 14 55 3 32 62 7 50 70 1 16 56 2 34 63 5 52 70 9 Figure 5 4 Intel Core 2 Quad Processor Q9000S and Q8000S Series Thermal Profile y 0 41x 49 6 45 50 55 60 65 70 75 80 0 10 20 30 4...

Страница 81: ...l manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active When the Thermal Monitor feature is enabled and a high temperature situation exists i e TCC is active the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor typically 30 50 Clocks often will not be off for more than 3 0...

Страница 82: ...ting point represents the normal operating condition for the processor Under this condition the core frequency to FSB multiple utilized by the processor is that contained in the CLK_GEYSIII_STAT MSR and the VID is that specified in Table 2 3 These parameters represent normal system operation The second operating point consists of both a lower operating frequency and voltage When the TCC is activat...

Страница 83: ...software usage of this mechanism to limit the processor temperature If bit 4 of the ACPI P_CNT Control Register located in the processor IA32_THERM_CONTROL MSR is written to a 1 the processor will immediately reduce its power consumption via modulation starting and stopping of the internal core clock independent of the processor temperature When using On Demand mode the duty cycle of the clock mod...

Страница 84: ...rature situations The PROCHOT signal is bi directional in that it can either signal when the processor either core has reached its maximum operating temperature or be driven from an external source to activate the TCC The ability to activate the TCC via PROCHOT can provide a means for thermal protection of system components Bi directional PROCHOT can allow VR thermal designs to target maximum sust...

Страница 85: ...tivation on PECI Based Systems Fan speed control solutions based on PECI utilize a TCONTROL value stored in the processor IA32_TEMPERATURE_TARGET MSR The TCONTROL MSR uses the same offset temperature format as PECI though it contains no sign bit Thermal management devices should infer the TCONTROL value as negative Thermal management algorithms should utilize the relative temperature value deliver...

Страница 86: ... power on RESET and during RESET assertion PECI is not assured to provide reliable thermal data System designs should implement a default power on condition that ensures proper processor operation during the time frame when reliable data is not available via PECI To protect platforms from potential operational or safety issues due to an abnormal condition on PECI the Host controller should take ac...

Страница 87: ...ding option 2 Address signals not identified in this table as configuration options should not be asserted during RESET 3 Disabling of any of the cores within a processor must be handled by configuring the EXT_CONFIG Model Specific Register MSR This MSR allows for the disabling of a single core per die within the processor package 6 2 Clock Control and Low Power States The processor allows the use...

Страница 88: ...ocessor continues normal operation The halted core will transition to the Normal state upon the occurrence of SMI INIT or LINT 1 0 NMI INTR RESET will cause the processor to immediately initialize itself The return from a System Management Interrupt SMI handler can be to either Normal Mode or the HALT Power Down state See the Intel Architecture Software Developer s Manual Volume 3B System Programm...

Страница 89: ...ransition the VID to the original value and then change the bus ratio back to the original value 6 2 3 Stop Grant and Extended Stop Grant States The processor supports the Stop Grant and Extended Stop Grant states The Extended Stop Grant state is a feature that must be configured and enabled using BIOS Refer to the sections below for details about the Stop Grant and Extended Stop Grant states 6 2 ...

Страница 90: ...p transaction the processor enters the HALT Snoop State Stop Grant Snoop state The processor will stay in this state until the snoop on the FSB has been serviced whether by the processor or another agent on the FSB After the snoop is serviced the processor will return to the Stop Grant state or HALT powerdown state as appropriate 6 2 4 2 Extended HALT Snoop State Extended Stop Grant Snoop State Th...

Страница 91: ...s follows Deep Sleep entry the system clock chip may stop tristate BCLK within two BCLKs of DPSLP assertion It is permissible to leave BCLK running during Deep Sleep Deep Sleep exit the system clock chip must drive BCLK to differential DC levels within 2 3 ns of DPSLP de assertion and start toggling BCLK within 10 BCLK periods To re enter the Sleep state the DPSLP pin must be deasserted BCLK can b...

Страница 92: ...d voltage This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system Note that the front side bus is not altered only the internal core frequency is changed In order to run at reduced power consumption the voltage is altered in step with the bus ratio The following are key features of Enhanced Intel S...

Страница 93: ... with the processor Refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 for further guidance Note Unless otherwise noted all figures in this chapter are dimensioned in millimeters and inches in brackets Figure 7 1 shows a mechanical representation of a boxed processor Note Drawings in this section reflect only the specifications on the Intel boxed processor product Th...

Страница 94: ...r with assembled fan heatsink are shown in Figure 7 2 Side View and Figure 7 3 Top View The airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and system designs Airspace requirements are shown in Figure 7 7 and Figure 7 8 Note that some figures have centerlines shown marked with alphabetic designations to clarify relative dimensioning NOTES 1 D...

Страница 95: ...sor to draw power from a power header on the baseboard The power cable connector and pinout are shown in Figure 7 5 Baseboards must provide a matched power header to support the boxed processor Table 7 1 contains specifications for the input and output signals at the fan heatsink connector The fan heatsink outputs a SENSE signal which is an open collector output that pulses at a rate of 2 pulses p...

Страница 96: ...n Typ Max Unit Notes 12 V 12 volt fan power supply 11 4 12 12 6 V IC Maximum fan steady state current draw Average fan steady state current draw Maximum fan start up current draw Fan start up current draw maximum duration 1 2 0 5 2 2 1 0 A A A Second SENSE SENSE frequency 2 pulses per fan revolution 1 NOTES 1 Baseboard should pull this pin up to 5 V with a resistor CONTROL 21 25 28 kHz 2 3 2 Open ...

Страница 97: ...od thermal management For the boxed processor fan heatsink to operate properly it is critical that the airflow provided to the fan heatsink is unimpeded Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked Blocking the airflow to the fan heatsink reduces the coo...

Страница 98: ...s temperature specification see Chapter 5 is the responsibility of the system integrator The motherboard must supply a constant 12 V to the processor s power header to ensure proper operation of the variable speed fan for the boxed processor Refer to Table 7 1 for the specific requirements Figure 7 9 Boxed Processor Fan Heatsink Set Points Table 7 2 Fan Heatsink Power and Signal Specifications Box...

Страница 99: ...in baseboard designs Under thermistor controlled mode the fan RPM is automatically varied based on the Tinlet temperature measured by a thermistor located at the fan inlet For more details on specific motherboard requirements for 4 wire based fan speed control see the appropriate Thermal and Mechanical Design Guidelines See Section 1 2 7 5 Boxed Intel Core 2 Extreme Processor QX9650 Specifications...

Страница 100: ...fan heatsink weight will complies with the socket specifications See Chapter 5 and the appropriate Thermal and Mechanical Design Guidelines See Section 1 2 for details on the processor weight and heatsink requirements Figure 7 10 Space Requirements for the Boxed Processor side view Figure 7 11 Boxed Processor Fan Heatsink Airspace Keepout Requirements side 1 view ...

Страница 101: ...Datasheet 103 Boxed Processor Specifications Figure 7 12 Boxed Processor Fan Heatsink Airspace Keepout Requirements side 2 view ...

Страница 102: ...Boxed Processor Specifications 104 Datasheet ...

Страница 103: ...ssor The LAI lands plug into the processor socket while the processor lands plug into a socket on the LAI Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer The maximum volume occupied by the LAI known as the keepout volume as well as the cable egress restrictions should be obtained from the logic analyzer vendor System ...

Страница 104: ...Debug Tools Specifications 106 Datasheet ...

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