Intel CORE 2 DUO E4000 - 3-2008, Техническое описание

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Land Listing and Signal Descriptions
Datasheet 75
LOCK#
Input/
Output
LOCK# indicates to the system that a transaction must occur
atomically. This signal must connect the appropriate pins/lands of
all processor FSB agents. For a locked sequence of transactions,
LOCK# is asserted from the beginning of the first transaction to the
end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of
the processor FSB, it will wait until it observes LOCK# de-asserted.
This enables symmetric agents to retain ownership of the processor
FSB throughout the bus locked operation and ensure the atomicity
of lock.
MSID[1:0] Output
These signals indicate the Market Segment for the processor. Refer
to
Table 3 for additional information.
PECI
Input/
Output
PECI is a proprietary one-wire bus interface. See Section 5.4 for
details.
PROCHOT#
Input/
Output
As an output, PROCHOT# (Processor Hot) will go active when the
processor temperature monitoring sensor detects that the processor
has reached its maximum safe operating temperature. This
indicates that the processor Thermal Control Circuit (TCC) has been
activated, if enabled. As an input, assertion of PROCHOT# by the
system will activate the TCC, if enabled. The TCC will remain active
until the system de-asserts PROCHOT#. See
Section 5.2.4 for more
details.
PWRGOOD Input
PWRGOOD (Power Good) is a processor input. The processor
requires this signal to be a clean indication that the clocks and
power supplies are stable and within their specifications. ‘Clean’
implies that the signal will remain low (capable of sinking leakage
current), without glitches, from the time that the power supplies are
turned on until they come within specification. The signal must then
transition monotonically to a high state. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable
before a subsequent rising edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor; it is used
to protect internal circuits against voltage sequencing issues. It
should be driven high throughout boundary scan operation.
REQ[4:0]#
Input/
Output
REQ[4:0]# (Request Command) must connect the appropriate pins/
lands of all processor FSB agents. They are asserted by the current
bus owner to define the currently active transaction type. These
signals are source synchronous to ADSTB0#.
RESET# Input
Asserting the RESET# signal resets the processor to a known state
and invalidates its internal caches without writing back any of their
contents. For a power-on Reset, RESET# must stay active for at
least one millisecond after V
CC
and BCLK have reached their proper
specifications. On observing active RESET#, all FSB agents will de-
assert their outputs within two clocks. RESET# must not be kept
asserted for more than 10 ms while PWRGOOD is asserted.
A number of bus signals are sampled at the active-to-inactive
transition of RESET# for power-on configuration. These
configuration options are described in the
Section 6.1 .
This signal does not have on-die termination and must be
terminated on the system board.
Table 26. Signal Description (Sheet 1 of 9)
Name Type Description