Intel BX80619I73820, Руководство по конструкции

Страница: 51 / 124

Thermal/Mechanical Specifications and Design Guide 51
Thermal Management Specifications
failure. The system thermal design should allow the power delivery circuitry to operate
within its temperature specification even while the processor is operating at its Thermal
Design Power.
With a properly designed and characterized thermal solution, it is anticipated that
PROCHOT_N will be asserted for very short periods of time when running the most
power intensive applications. An under-designed thermal solution that is not able to
prevent excessive assertion of PROCHOT_N in the anticipated ambient environment
may cause a noticeable performance loss. Refer to the appropriate platform design
guide and for details on implementing the bi-directional PROCHOT_N feature.
6.2.5 THERMTRIP_N Signal
Regardless of whether Adaptive Thermal Monitor is enabled, in the event of a
catastrophic cooling failure, the processor will automatically shut down when the silicon
has reached an elevated temperature (refer to the THERMTRIP_N definition in the
Datasheet). At this point, the THERMTRIP_N signal will go active and stay active.
THERMTRIP_N activation is independent of processor activity. If THERMTRIP_N is
asserted, all processor supplies (V
CC
, V
TTA
, V
TTD
, V
SA
, V
CCPLL
, V
CCD
) must be removed
within the timeframe which is TBD at this point. The temperature at which
THERMTRIP_N asserts is not user configurable and is not software visible.
6.3 Platform Environment Control Interface (PECI)
6.3.1 Introduction
PECI uses a single wire for self-clocking and data transfer. The bus requires no
additional control lines. The physical layer is a self-clocked one-wire bus that begins
each bit with a driven, rising edge from an idle level near zero volts. The duration of the
signal driven high depends on whether the bit value is a logic ‘0’ or logic ‘1’. PECI also
includes variable data transfer rate established with every message. In this way, it is
highly flexible even though underlying logic is simple.
The interface design was optimized for interfacing to Intel processor and chipset
components in both single processor and multiple processor environments. The single
wire interface provides low board routing overhead for the multiple load connections in
the congested routing area near the processor and chipset components. Bus speed,
error checking, and low protocol overhead provides adequate link bandwidth and
reliability to transfer critical device operating conditions and configuration information.
The PECI bus offers:
• A wide speed range from 2 Kbps to 2 Mbps
• CRC check byte used to efficiently and atomically confirm accurate data delivery
• Synchronization at the beginning of every message minimizes device timing
accuracy requirements.