Errata
Intel
®
Core™2 Extreme Quad-Core Processor QX6000
Δ
Sequence and
47
Intel
®
Core™2 Quad Processor Q6000
Δ
Sequence
Specification Update
AK75.
In Single-Stepping on Branches Mode, the BS Bit in the Pending-
Debug-Exceptions Field of the Guest State Area will be Incorrectly
Set by VM Exit on a MOV to CR8 Instruction
Problem:
In a system supporting Intel
®
Virtualization Technology, the BS bit (bit 14 of
the Pending-Debug-Exceptions field) in the guest state area will be incorrectly
set when all of the following conditions occur:
•
The processor is running in VMX non-root as a 64 bit mode guest;
•
The “CR8-load existing” VM-execution control is 0 and the “use TPR shadow” VM-
execution is 1;
•
Both BTF (Single-Step On Branches, bit 1) of the IA32_DEBUGCTL MSR (1D9H)
Register and the TF (Trap Flag, bit 8) of the RFLAGS Register are set;
•
“MOV CR8, reg” attempts to program a TPR (Task Priority Register) value that is
below the TPR threshold and causes a VM exit.
Implication:
A Virtual-Machine will sample the BS bit and will incorrectly inject a Single-
Step trap to the guest.
Workaround:
A Virtual-Machine Monitor must manually disregard the BS bit in the Guest
State Area in case of a VM exit due to a TPR value below the TPR threshold.
Status:
For the steppings affected, see the Summary Tables of Changes.
AK76.
B0–B3 Bits in DR6 May Not be Properly Cleared After Code Breakpoint
Problem:
B0-B3 bits (breakpoint conditions detect flags, bits [3:0]) in DR6 may not be
properly cleared when the following sequence happens:
1)
POP instruction to SS (Stack Segment) selector;
2)
Next instruction is FP (Floating Point) that gets FP assist followed by code
breakpoint.
Implication:
B0–B3 bits in DR6 may not be properly cleared.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AK77.
BTM/BTS Branch-From Instruction Address May be Incorrect for
Software Interrupts.
Problem:
When BTM (Branch Trace Message) or BTS (Branch Trace Store) is enabled, a
software interrupt may result in the overwriting of BTM/BTS branch-from
instruction address by the LBR (Last Branch Record) branch-from instruction
address.
Implication:
A BTM/BTS branch-from instruction address may get corrupted for software
interrupts.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
