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Errata

Specification Update

AA30.

During an Enhanced HALT or Enhanced Intel SpeedStep

Technology

Ratio Transition the System May Hang

Problem:

The BNR signal may not function properly during an Enhanced HALT or

Enhanced Intel SpeedStep Technology ratio transition.

Implication:

The system may hang due to incorrect BNR signaling.

Workaround:

It is possible for the BIOS to contain a workaround for this erratum.

Status:

For the steppings affected, see the

Summary Tables of Changes.

AA31.

L2 Cache ECC Machine Check Errors May be erroneously Reported

after an Asynchronous RESET# Assertion

Problem:

Machine check status MSRs may incorrectly report the following L2 Cache

ECC machine-check errors when cache transactions are in-flight and RESET#

is asserted:

•Instruction Fetch Errors (IA32_MC2_STATUS with MCA error code 153)

•L2 Data Write Errors (IA32_MC1_STATUS with MCA error code 145)

Implication:

Uncorrected or corrected L2 ECC machine check errors may be erroneously

reported. Intel has not observed this erratum on any commercially available

system.

Workaround:

When a real run-time L2 Cache ECC Machine Check occurs, a corresponding

valid error will normally be logged in the IA32_MC0_STATUS register. BIOS

may clear IA32_MC2_STATUS and/or IA32_MC1_STATUS for these specific

errors when IA32_MC0_STATUS does not have its VAL flag set.

Status:

For the steppings affected, see the

Summary Tables of Changes

AA32.

VMCALL to Activate Dual-monitor Treatment of SMIs and SMM

Ignores Reserved Bit settings in VM-exit Control Field

Problem:

Processors supporting Intel

Virtualization Technology can execute VMCALL

from within the Virtual Machine Monitor (VMM) to activate dual-monitor

treatment of SMIs and SMM. Due to this erratum, if reserved bits are set to

values inconsistent with VMX Capability MSRs, VMCALL may not VMFail.

Implication:

VMCALL executed to activate dual-monitor treatment of SMIs and SMM may

not VMFail due to incorrect reserved bit settings in VM-Exit control field.

Workaround:

Software should ensure that all VMCS reserved bits are set to values

consistent with VMX Capability MSRs.

Status:

For the steppings affected, see the

Summary Tables of Changes.

Содержание 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU

Страница 1: ...equence and Intel Pentium Processor Extreme Edition 955 965 Specification Update On 65 nm Process in the 775 land LGA Package supporting Intel 64 Architecture and Intel Virtualization Technology May 2...

Страница 2: ...ts ht hyperthreading_more htm for more information including details on which processors support HT Technology 64 bit computing on Intel architecture requires a computer system with a processor chipse...

Страница 3: ...Contents Contents 3 Revision History 4 Preface 5 Summary Tables of Changes 7 General Information 13 Identification Information 14 Errata 16 Specification Changes 32 Specification Clarifications 33 Do...

Страница 4: ...AA34 added C1 step April 2006 007 Added Pentium D processor 960 Out of Cycle May 1 2006 008 Added Erratum AA35 May 2006 009 Added Errata AA36 41 June 2006 010 Added Rtt Specification change July 2006...

Страница 5: ...sor Extreme Edition 955 965 Datasheet 310306 003 Related Documents Document Title Document Number Intel 64 and IA 32 Architectures Software Developer s Manual Volume 1 Basic Architecture document 2536...

Страница 6: ...me that all errata documented for that stepping are present on all devices Specification Changes are modifications to the current published specifications These changes will be incorporated in the nex...

Страница 7: ...nges as noted This table uses the following notations Codes Used in Summary Table Stepping X Erratum Specification Change or Clarification that applies to this stepping No mark or Blank Box This errat...

Страница 8: ...el Xeon processor with 800 MHz system bus 1 MB and 2 MB L2 cache versions T Mobile Intel Pentium 4 processor M U 64 bit Intel Xeon processor MP with up to 8MB L3 cache V Mobile Intel Celeron processor...

Страница 9: ...dual core processor E1000 series AAD Intel Core 2 Extreme Processor QX9775 AAE Intel Atom processor Z5xx series NO B1 C1 D0 Plan ERRATA AA1 X X X No Fix Locks and SMC Detection May Cause the Processo...

Страница 10: ...et Probe Event in the Presence of a Specific Type of VM Exit AA18 X X Fixed VM EXIT Due to TPR shadow Below Threshold May Improperly Set and Cause Blocking by STI actions AA19 X X X No Fix Two Correct...

Страница 11: ...Fault When the Upper 8 Bytes of Segment Selector Is Loaded from a Far Jump through a Call Gate via the Local Descriptor Table AA38 X X X No Fix The Processor May Issue Front Side Bus Transactions up...

Страница 12: ...tion Update Number Plan SPECIFICATION CLARIFICATIONS There are no Specification Clarification in this Specification Update revision Number Plan DOCUMENTATION CHANGES There are no Documentation Changes...

Страница 13: ...eral Information Specification Update 13 General Information Figure 1 Intel Pentium D Processor 900 Sequence Package Top Markings Figure 2 Intel Pentium Processor Extreme Edition 965 Package Top Marki...

Страница 14: ...xecuted with a 2 in the EAX register Refer to the Intel Processor Identification and the CPUID Instruction Application Note AP 485 Table 1 Intel Pentium D Processor 900 Sequence and Intel Pentium Proc...

Страница 15: ...dition 965 3 73GHz 1066MHz 775 land LGA 2 4 6 SL9KB D0 2M x 2 0F65h 915 2 80GHz 800MHz 775 Land LGA 1 3 SL9KA D0 2M x 2 0F65h 925 3 00GHz 800MHz 775 Land LGA 1 3 SL9QR D0 2M x 2 0F65h 935 3 20GHz 800M...

Страница 16: ...ilable software Workaround None identified Status For the steppings affected see the Summary Tables of Changes AA2 Memory Aliasing of Pages As Uncacheable Memory Type and Write Back WB May Hang the Sy...

Страница 17: ...rted by CPUID instruction 0x8000008 This erratum applies whenever PAE is enabled Implication Software that sets the upper address bits on a MOV CR3 instruction and expects a fault may fail This erratu...

Страница 18: ...ectly zero upper 32 bits of RSP Implication A Push of ESP in compatibility mode will zero the upper 32 bits of RSP Due to this erratum this instruction fault may change the contents of RSP This erratu...

Страница 19: ...that would cross BTS PEBS absolute maximum will also continue past the end of the virtual address space A BTS PEBS record can be written that will wrap at the 4G boundary IA32 or 2 64 boundary EM64T...

Страница 20: ...available software Workaround Do not use strings larger than 4 GB Status For the steppings affected see the Summary Tables of Changes AA13 A 64 Bit Value of Linear Instruction Pointer LIP May be Repor...

Страница 21: ...set and the use TPR shadow bit is not set a MOV from CR8 instruction executed by a Virtual Machine Extensions VMX guest that causes a VM exit may generate an unexpected memory access Implication When...

Страница 22: ...Below Threshold May Improperly Set and Cause Blocking by STI actions Problem In a system supporting Intel Virtualization Technology and Intel EM64T the blocking by STI bit of the interruptibility stat...

Страница 23: ...omatic mode of the TCC Implication When this erratum occurs the processor may hang Workaround If use of the on demand mode of the processor s TCC is desired in conjunction with STPCLK modulation then...

Страница 24: ...a VM exit entry which loads the affected MSR Workaround It is possible for the BIOS to contain a workaround for this erratum Status For the steppings affected see the Summary Tables of Changes AA25 W...

Страница 25: ...ible for the BIOS to contain a workaround for this erratum Status For the steppings affected see the Summary Tables of Changes AA28 The Execution of VMPTRLD or VMREAD May Cause an Unexpected Memory Ac...

Страница 26: ...l has not observed this erratum on any commercially available system Workaround When a real run time L2 Cache ECC Machine Check occurs a corresponding valid error will normally be logged in the IA32_M...

Страница 27: ...20M is normally only used with the first megabyte of memory Status For the steppings affected see the Summary Tables of Changes AA34 Writing Shared Unaligned Data that Crosses a Cache Line without Pro...

Страница 28: ...set and the interrupt handler s stack is misaligned In IA 32e mode RSP is aligned to a 16 byte boundary before pushing the stack frame Implication In IA 32e mode under the conditions given above an IR...

Страница 29: ...he processor may log FSB protocol signal integrity machine checks if transactions are allowed to occur during RESET assertions Workaround BIOS may clear FSB protocol signal integrity machine checks fo...

Страница 30: ...quiring resources to also execute a lock Implication This erratum may cause system hang or unpredictable system behavior This erratum has not been observed with commercially available software Workaro...

Страница 31: ...r Due to this erratum the expected VMX aborts may not occur and instead the VM Exit will occur normally The conditions required to observe this erratum are a VM entry that returns from SMM with the IA...

Страница 32: ...processor Extreme Edition 955 965 documentation Intel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different pro...

Страница 33: ...section apply to the following documents Intel Pentium D Processor 900 Sequence and Intel Pentium Processor Extreme Edition 955 965 Datasheet All Specification Clarifications will be incorporated into...

Страница 34: ...propriate Pentium D processor 900 sequence and Pentium processor Extreme Edition 955 965 documentation Note Documentation changes for Intel 64 and IA 32 Architecture Software Developer s Manual volume...

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